Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8171262 | Method and apparatus for clearing hazards using jump instructions | Niels Gram Jeppesen | 2012-05-01 |
| 7925864 | Method and apparatus for binding shadow registers to vectored interrupts | — | 2011-04-12 |
| 7853777 | Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions | Darren M. Jones, Ryan C. Kinter, Sanjay Vishin | 2010-12-14 |
| 7724261 | Processor having a compare extension of an instruction set architecture | Radhika Thekkath, Ying-wai Ho, Chandlee B. Harrell | 2010-05-25 |
| 7552261 | Configurable prioritization of core generated interrupts | — | 2009-06-23 |
| 7487339 | Method and apparatus for binding shadow registers to vectored interrupts | — | 2009-02-03 |
| 7242414 | Processor having a compare extension of an instruction set architecture | Radhika Thekkath, Ying-wai Ho, Chandlee B. Harrell | 2007-07-10 |
| 7185183 | Atomic update of CPO state | — | 2007-02-27 |
| 7181600 | Read-only access to CPO registers | — | 2007-02-20 |
| 7065675 | System and method for speeding up EJTAG block data transfers | Radhika Thekkath, Scott M. McCoy, Franz Treue, Morten Zilmer | 2006-06-20 |
| 7000095 | Method and apparatus for clearing hazards using jump instructions | Niels Gram Jeppesen | 2006-02-14 |
| 6732259 | Processor having a conditional branch extension of an instruction set architecture | Radhika Thekkath, Ying-wai Ho, Chandlee B. Harrell | 2004-05-04 |
| 6714197 | Processor having an arithmetic extension of an instruction set architecture | Radhika Thekkath, Ying-wai Ho, Chandlee B. Harrell | 2004-03-30 |
| 6681283 | Coherent data apparatus for an on-chip split transaction system bus | Radhika Thekkath | 2004-01-20 |
| 6651156 | Mechanism for extending properties of virtual memory pages by a TLB | David A. Courtright, Lawrence Henry Hudepohl, Kevin D. Kissell | 2003-11-18 |
| 6604159 | Data release to reduce latency in on-chip system bus | Radhika Thekkath | 2003-08-05 |
| 6493776 | Scalable on-chip system bus | David A. Courtright, Vidya Rajagopalan, Radhika Thekkath | 2002-12-10 |
| 6490642 | Locked read/write on separate address/data bus using write barrier | Radhika Thekkath | 2002-12-03 |
| 6240508 | Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory read | John F. Brown, William R. Wheeler | 2001-05-29 |
| 5802272 | Method and apparatus for tracing unpredictable execution flows in a trace buffer of a high-speed computer system | Richard L. Sites, Sharon E. Perl, David G. Conroy | 1998-09-01 |
| 5764885 | Apparatus and method for tracing data flows in high-speed computer systems | Richard L. Sites, Sharon E. Perl, David G. Conroy | 1998-06-09 |
| 5579504 | Multi-processor computer system having shared memory, private cache memories, and invalidate queues having valid bits and flush bits for serializing transactions | Michael A. Callander, W. Hugh Durdan | 1996-11-26 |
| 5542058 | Pipelined computer with operand context queue to simplify context-dependent execution flow | John E. Brown, John H. Edmondson, Debra Bernstein | 1996-07-30 |
| 5481689 | Conversion of internal processor register commands to I/O space addresses | Rebecca L. Stamm | 1996-01-02 |
| 5450349 | Computer system performance evaluation system and method | John F. Brown, Richard L. Sites | 1995-09-12 |