Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7305526 | Method, system, and program for transferring data directed to virtual memory addresses to a device memory | Michael T. Benhase, Robert Alan Cargnoni, James Stephen Fields, Jr., Bruce Mealey | 2007-12-04 |
| 7171445 | Fixed snoop response time for source-clocked multiprocessor busses | James Allen, Alvan W. Ng | 2007-01-30 |
| 6968431 | Method and apparatus for livelock prevention in a multiprocessor system | — | 2005-11-22 |
| 6915415 | Method and apparatus for mapping software prefetch instructions to hardware prefetch logic | Francis Patrick O'Connell, David Scott Ray | 2005-07-05 |
| 6587930 | Method and system for implementing remstat protocol under inclusion and non-inclusion of L1 data in L2 cache to prevent read-read deadlock | Sanjay Deshpande, Peter Steven Lenk | 2003-07-01 |
| 6578130 | Programmable data prefetch pacing | Brian D. Barrick, Brian Patrick Hanley | 2003-06-10 |
| 6574712 | Software prefetch system and method for predetermining amount of streamed data | James Allan Kahle, Francis Patrick O'Connell, David Scott Ray, Edward John Silha, Joel M. Tendler | 2003-06-03 |
| 6535962 | System and method for prefetching data using a hardware prefetch mechanism | Francis Patrick O'Connell, David Scott Ray | 2003-03-18 |
| 6460115 | System and method for prefetching data to multiple levels of cache including selectively using a software hint to override a hardware prefetch mechanism | James Allan Kahle, Francis Patrick O'Connell, David Scott Ray, Edward John Silha, Joel M. Tendler | 2002-10-01 |
| 6446167 | Cache prefetching of L2 and L3 | Francis Patrick O'Connell, David Scott Ray | 2002-09-03 |
| 6446170 | Efficient store machine in cache based microprocessor | Kin Shing Chan, Dwain A. Hicks, Shih-Hsiung S. Tung | 2002-09-03 |
| 6298417 | Pipelined cache memory deallocation and storeback | Kin Shing Chan, Dwain A. Hicks, Shih-Hsiung S. Tung | 2001-10-02 |
| 6202128 | Method and system for pre-fetch cache interrogation using snoop port | Kin Shing Chan, Dwain A. Hicks, Peichun Peter Liu, Shih-Hsiung S. Tung | 2001-03-13 |
| 6178493 | Multiprocessor stalled store detection | Peter Steven Lenk, Robert J. Reese, Michael Thomas Vaden | 2001-01-23 |
| 6085291 | System and method for selectively controlling fetching and prefetching of data to a processor | Dwain A. Hicks, David Scott Ray, Shih-Hsiung S. Tung | 2000-07-04 |
| 5860150 | Instruction pre-fetching of a cache line within a processor | Kevin Arthur Chiarot, Era K. Nangia, Milford John Peterson | 1999-01-12 |
| 5809529 | Prefetching of committed instructions from a memory to an instruction cache | — | 1998-09-15 |
| 5787478 | Method and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchy | Dwain A. Hicks, Peichun Peter Liu, Rajinder Paul Singh | 1998-07-28 |
| 5758119 | System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache | Trinh Huy Nguyen, Robert J. Reese, Michael Thomas Vaden | 1998-05-26 |
| 5740399 | Modified L1/L2 cache inclusion for aggressive prefetch | Trinh Huy Nguyen, Robert J. Reese, Michael Thomas Vaden | 1998-04-14 |
| 5737565 | System and method for diallocating stream from a stream buffer | — | 1998-04-07 |
| 5721864 | Prefetching instructions between caches | Kevin Arthur Chiarot, Era K. Nangia, Milford John Peterson | 1998-02-24 |
| 5664147 | System and method that progressively prefetches additional lines to a distributed stream buffer as the sequentiality of the memory accessing is demonstrated | — | 1997-09-02 |
| 5623632 | System and method for improving multilevel cache performance in a multiprocessing system | Peichun Peter Liu, Robert J. Reese | 1997-04-22 |
| 4571671 | Data processor having multiple-buffer adapter between a system channel and an input/output bus | Charles S. Burns, Michael Crabtree, Dwight A. Gourneau, Scott W. Hinkel, George A. Lerom | 1986-02-18 |