Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12118342 | Applying a code update to a target system from a personal communication device | Michael J. Koester, Kevin L. Miner, Camvu Pham | 2024-10-15 |
| 11775289 | Source code development interface for storage management | Tan Q. Nguyen | 2023-10-03 |
| 11409759 | Data dump formatting utilizing dynamically created control structures | Harshpreet Singh | 2022-08-09 |
| 11163587 | Interface that enables streamlined user-friendly initiation/control of modifications and/or initial program loading (IPL) of a target system | Kevin L. Miner, Camvu Pham, Bard A. Doster | 2021-11-02 |
| 10691549 | System managed facilitation of backup of dataset before deletion | Michael J. Koester, Kevin L. Miner, Steven Huntington | 2020-06-23 |
| 10564874 | Dynamically managing a table of contents | Michael J. Koester, Kevin L. Miner, Carrie J. Van Noorden | 2020-02-18 |
| 10242078 | Data dump formatting utilizing dynamically created control structures | Harshpreet Singh | 2019-03-26 |
| 9996294 | Dynamically managing a table of contents | Michael J. Koester, Kevin L. Miner, Carrie J. Van Noorden | 2018-06-12 |
| 9940903 | System and method for managing, publishing and manipulating data objects | John Najarian, Gerald Abrahamian, Darren Hand, Timothy MOHN, Lou R. Houlemarde +1 more | 2018-04-10 |
| 9141391 | Data processing system with latency tolerance execution | Thang M. Tran | 2015-09-22 |
| 9135014 | Data processing system with latency tolerance execution | Thang M. Tran | 2015-09-15 |
| 9110656 | Systems and methods for handling instructions of in-order and out-of-order execution queues | Thang M. Tran | 2015-08-18 |
| 8966229 | Systems and methods for handling instructions of in-order and out-of-order execution queues | Thang M. Tran | 2015-02-24 |
| 8145942 | Methods and systems for troubleshooting remote systems through recreation of remote system scenarios | — | 2012-03-27 |
| 8117618 | Forward progress mechanism for a multithreaded processor | David C. Holloway, Michael D. Snyder, Gary L. Whisenhunt | 2012-02-14 |
| 7805581 | Multiple address and arithmetic bit-mode data processing device and methods thereof | Michael D. Snyder, David C. Holloway, Sergio Schuler, Gary L. Whisenhunt | 2010-09-28 |
| 7698353 | Floating point normalization and denormalization | Dimitri Tan | 2010-04-13 |
| 6973471 | Method and apparatus for implementing signed multiplication of operands having differing bit widths without sign extension of the multiplicand | — | 2005-12-06 |
| 5758119 | System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache | Michael John Mayfield, Robert J. Reese, Michael Thomas Vaden | 1998-05-26 |
| 5740399 | Modified L1/L2 cache inclusion for aggressive prefetch | Michael John Mayfield, Robert J. Reese, Michael Thomas Vaden | 1998-04-14 |
| 5274646 | Excessive error correction control | Thomas M. Brey, Matthew A. Krygowski, Bruce L. McGilvray, William Wu Shen, Arthur J. Sutton | 1993-12-28 |