Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11409663 | Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes | David Campbell | 2022-08-09 |
| 11221963 | Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB) | David Campbell | 2022-01-11 |
| 11157415 | Operation of a multi-slice processor implementing a unified page walk cache | Jonathan H. Raymond, George W. Rohrbaugh, III, Shih-Hsiung S. Tung | 2021-10-26 |
| 11061810 | Virtual cache mechanism for program break point register exception handling | David Campbell, David A. Hrusecky, Bryan Lloyd | 2021-07-13 |
| 10915459 | Methods and systems for optimized translation of a virtual address having multiple virtual address portions using multiple translation lookaside buffer (TLB) arrays for variable page sizes | David Campbell | 2021-02-09 |
| 10824494 | Operation of a multi-slice processor implementing exception handling in a nested translation environment | Jonathan H. Raymond, Shih-Hsiung S. Tung | 2020-11-03 |
| 10740248 | Methods and systems for predicting virtual address | David Campbell, Christian Jacobi | 2020-08-11 |
| 10649778 | Performance optimized congruence class matching for multiple concurrent radix translations | David Campbell, Christian Jacobi, Kerey Michelle Tassin | 2020-05-12 |
| 10621106 | Methods and systems for incorporating non-tree based address translation into a hierarchical translation lookaside buffer (TLB) | David Campbell | 2020-04-14 |
| 10534715 | Operation of a multi-slice processor implementing a unified page walk cache | Jonathan H. Raymond, George W. Rohrbaugh, III, Shih-Hsiung S. Tung | 2020-01-14 |
| 10042691 | Operation of a multi-slice processor implementing exception handling in a nested translation environment | Jonathan H. Raymond, Shih-Hsiung S. Tung | 2018-08-07 |
| 7769985 | Load address dependency mechanism system and method in a high frequency, low power processor system | Brian D. Barrick, Kimberly M. Fernsler, David Scott Ray, David Shippy, Takeki Osanai | 2010-08-03 |
| 7730290 | Systems for executing load instructions that achieve sequential load consistency | Brian D. Barrick, Kimberly M. Fernsler, Takeki Osanai, David Scott Ray | 2010-06-01 |
| 7464242 | Method of load/store dependencies detection with dynamically changing address length | Brian D. Barrick, Takeki Osanai, David Scott Ray | 2008-12-09 |
| 7376816 | Method and systems for executing load instructions that achieve sequential load consistency | Brian D. Barrick, Kimberly M. Fernsler, Takeki Osanai, David Scott Ray | 2008-05-20 |
| 7363468 | Load address dependency mechanism system and method in a high frequency, low power processor system | Brian D. Barrick, Kimberly Marie Fensler, David Scott Ray, David Shippy, Takeki Osanai | 2008-04-22 |
| 7302527 | Systems and methods for executing load instructions that avoid order violations | Brian D. Barrick, Kimberly M. Fernsler, Takeki Osanai, David Scott Ray | 2007-11-27 |
| 7302530 | Method of updating cache state information where stores only read the cache state information upon entering the queue | Brian D. Barrick, Takeki Osanai | 2007-11-27 |
| 6604173 | System for controlling access to external cache memories of differing size | Hoichi Cheong, George McNeil Lattimore, Peichun Peter Liu | 2003-08-05 |
| 6446170 | Efficient store machine in cache based microprocessor | Kin Shing Chan, Michael John Mayfield, Shih-Hsiung S. Tung | 2002-09-03 |
| 6298417 | Pipelined cache memory deallocation and storeback | Kin Shing Chan, Michael John Mayfield, Shih-Hsiung S. Tung | 2001-10-02 |
| 6240487 | Integrated cache buffers | Pei-Chun Liu, Rajinder Paul Singh, Shih-Hsiung S. Tung, Kin Shing Chan | 2001-05-29 |
| 6202128 | Method and system for pre-fetch cache interrogation using snoop port | Kin Shing Chan, Peichun Peter Liu, Michael John Mayfield, Shih-Hsiung S. Tung | 2001-03-13 |
| 6085291 | System and method for selectively controlling fetching and prefetching of data to a processor | Michael John Mayfield, David Scott Ray, Shih-Hsiung S. Tung | 2000-07-04 |
| 5953351 | Method and apparatus for indicating uncorrectable data errors | Avery C. Topps | 1999-09-14 |