Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7769985 | Load address dependency mechanism system and method in a high frequency, low power processor system | Brian D. Barrick, Kimberly M. Fernsler, Dwain A. Hicks, David Scott Ray, David Shippy | 2010-08-03 |
| 7730290 | Systems for executing load instructions that achieve sequential load consistency | Brian D. Barrick, Kimberly M. Fernsler, Dwain A. Hicks, David Scott Ray | 2010-06-01 |
| 7725686 | Systems and methods for processing buffer data retirement conditions | Brian D. Barrick | 2010-05-25 |
| 7689776 | Method and system for efficient cache locking mechanism | Kimberly M. Fernsler | 2010-03-30 |
| 7631149 | Systems and methods for providing fixed-latency data access in a memory system having multi-level caches | Kenji Iwamura | 2009-12-08 |
| 7607059 | Systems and methods for improved scan testing fault coverage | — | 2009-10-20 |
| 7464242 | Method of load/store dependencies detection with dynamically changing address length | Brian D. Barrick, Dwain A. Hicks, David Scott Ray | 2008-12-09 |
| 7376816 | Method and systems for executing load instructions that achieve sequential load consistency | Brian D. Barrick, Kimberly M. Fernsler, Dwain A. Hicks, David Scott Ray | 2008-05-20 |
| 7363468 | Load address dependency mechanism system and method in a high frequency, low power processor system | Brian D. Barrick, Kimberly Marie Fensler, Dwain A. Hicks, David Scott Ray, David Shippy | 2008-04-22 |
| 7346624 | Systems and methods for processing buffer data retirement conditions | Brian D. Barrick | 2008-03-18 |
| 7302530 | Method of updating cache state information where stores only read the cache state information upon entering the queue | Brian D. Barrick, Dwain A. Hicks | 2007-11-27 |
| 7302527 | Systems and methods for executing load instructions that avoid order violations | Brian D. Barrick, Kimberly M. Fernsler, Dwain A. Hicks, David Scott Ray | 2007-11-27 |
| 7240183 | System and method for detecting instruction dependencies in multiple phases | Kenji Iwamura | 2007-07-03 |
| 6389527 | Microprocessor allowing simultaneous instruction execution and DMA transfer | Michael Raam, Toru Utsumi, Kamran Malik | 2002-05-14 |
| 6360298 | Load/store instruction control circuit of microprocessor and load/store instruction control method | Johnny K. Szeto, Kyle Satoshi Tsukamoto | 2002-03-19 |
| 6327665 | Processor with power consumption limiting function | — | 2001-12-04 |