Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411688 | Gather buffer management for unaligned and gather load operations | Bryan Lloyd, David A. Hrusecky, David Campbell | 2025-09-09 |
| 11755324 | Gather buffer management for unaligned and gather load operations | Bryan Lloyd, David A. Hrusecky, David Campbell | 2023-09-12 |
| 11687337 | Processor overriding of a false load-hit-store detection | Bryan Lloyd, Brian Chen | 2023-06-27 |
| 11379241 | Handling oversize store to load forwarding in a processor | Bryan Lloyd, Brian Chen, Robert A. Cordes, David A. Hrusecky | 2022-07-05 |
| 11321088 | Tracking load and store instructions and addresses in an out-of-order processor | Bryan Lloyd, Samuel David Kirchhoff, Brian Chen, David A. Hrusecky | 2022-05-03 |
| 11314510 | Tracking load and store instructions and addresses in an out-of-order processor | Bryan Lloyd, Samuel David Kirchhoff, Brian Chen, David A. Hrusecky | 2022-04-26 |
| 11263151 | Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations | David Campbell, Bryan Lloyd, David A. Hrusecky, Jeffrey A. Stuecheli, Guy L. Guthrie +4 more | 2022-03-01 |
| 10884740 | Synchronized access to data in shared memory by resolving conflicting accesses by co-located hardware threads | Derek E. Williams, Guy L. Guthrie, Hugh Shen | 2021-01-05 |
| 10564978 | Operation of a multi-slice processor with an expanded merge fetching queue | David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone, Brian W. Thompto | 2020-02-18 |
| 10037211 | Operation of a multi-slice processor with an expanded merge fetching queue | David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone, Brian W. Thompto | 2018-07-31 |
| 9916245 | Accessing partial cachelines in a data cache | Richard J. Eickemeyer, Guy L. Guthrie, David A. Hrusecky, Elizabeth A. McGlone | 2018-03-13 |
| 8898667 | Dynamically manage applications on a processing system | Lydia M. Do, Jason A. Cox, Michael L. Karm, Brian R. Mestan | 2014-11-25 |
| 8387050 | System and method to dynamically manage applications on a processing system | Lydia M. Do, Jason A. Cox, Michael L. Karm, Brian R. Mestan | 2013-02-26 |
| 7769985 | Load address dependency mechanism system and method in a high frequency, low power processor system | Brian D. Barrick, Dwain A. Hicks, David Scott Ray, David Shippy, Takeki Osanai | 2010-08-03 |
| 7739477 | Multiple page size address translation incorporating page size prediction | Jeffrey Powers Bradford, Jason N. Dale, Timothy H. Heil, James Allen Rose | 2010-06-15 |
| 7730290 | Systems for executing load instructions that achieve sequential load consistency | Brian D. Barrick, Dwain A. Hicks, Takeki Osanai, David Scott Ray | 2010-06-01 |
| 7689776 | Method and system for efficient cache locking mechanism | Takeki Osanai | 2010-03-30 |
| 7376816 | Method and systems for executing load instructions that achieve sequential load consistency | Brian D. Barrick, Dwain A. Hicks, Takeki Osanai, David Scott Ray | 2008-05-20 |
| 7302527 | Systems and methods for executing load instructions that avoid order violations | Brian D. Barrick, Dwain A. Hicks, Takeki Osanai, David Scott Ray | 2007-11-27 |
| 7284112 | Multiple page size address translation incorporating page size prediction | Jeffrey Powers Bradford, Jason N. Dale, Timothy H. Heil, James Allen Rose | 2007-10-16 |
| 7159095 | Method of efficiently handling multiple page sizes in an effective to real address translation (ERAT) table | Jason N. Dale, Jonathan James DeMent | 2007-01-02 |