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Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
RC

Robert A. Cordes — 28 Patents

IBM: 28 patents #3,689 of 70,183Top 6%
Austin, TX: #1,113 of 18,064 inventorsTop 7%
Texas: #4,355 of 125,132 inventorsTop 4%
Overall (All Time): #134,628 of 4,157,543Top 4%
28 Patents All Time
Robert A. Cordes has been granted 28 US patents while listed as an inventor at IBM. The first was granted in 2012 and the most recent in August 2024. Robert A. Cordes ranks #134,628 of 4,157,543 US inventors in our database (top 3.2%). Patent records list Robert A. Cordes in Austin, TX, US.

Patents per Year

Patents granted per year, 2012 to 2024Bar chart with a peak of 7 patents in 2018.peak 72012: 2 patents20122013: 2 patents20132017: 1 patents20172018: 7 patents20182019: 6 patents20192020: 2 patents20202021: 2 patents20212022: 4 patents20222023: 1 patents20232024: 1 patents2024

Issued Patents All Time

Showing 1–25 of 28 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12061909 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Salma Ayub, Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Dung Q. Nguyen +1 more 2024-08-13 $23,564,000
11734010 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Salma Ayub, Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Dung Q. Nguyen +1 more 2023-08-22 $5,113,000
11520704 Writing store data of multiple store operations into a cache line in a single cycle Bryan Lloyd 2022-12-06 $6,201,000
11379241 Handling oversize store to load forwarding in a processor Bryan Lloyd, Brian Chen, Kimberly M. Fernsler, David A. Hrusecky 2022-07-05 $7,280,000
11263151 Dynamic translation lookaside buffer (TLB) invalidation using virtually tagged cache for load/store operations David Campbell, Bryan Lloyd, David A. Hrusecky, Kimberly M. Fernsler, Jeffrey A. Stuecheli +4 more 2022-03-01 $6,542,000
11243773 Area and power efficient mechanism to wakeup store-dependent loads according to store drain merges Bryan Lloyd, David Campbell, Brian Chen 2022-02-08 $4,353,000
11150907 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Salma Ayub, Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Dung Q. Nguyen +1 more 2021-10-19 $2,168,000
10884742 Handling unaligned load operations in a multi-slice computer processor Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more 2021-01-05 $2,293,000
10831481 Handling unaligned load operations in a multi-slice computer processor Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more 2020-11-10 $848,000
10761854 Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor David A. Hrusecky, Elizabeth A. McGlone 2020-09-01 $3,521,000
10496406 Handling unaligned load operations in a multi-slice computer processor Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more 2019-12-03 $6,493,000
10409598 Handling unaligned load operations in a multi-slice computer processor Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more 2019-09-10 $4,978,000
10268518 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone 2019-04-23 $3,141,000
10255107 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone 2019-04-09 $2,400,000
10223266 Extended store forwarding for store misses without cache allocate Hung Q. Le, Brian W. Thompto 2019-03-05 $2,050,000
10169046 Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction Maarten J. Boersma, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto, Albert J. Van Norstrand, Jr. +1 more 2019-01-01
10133576 Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Salma Ayub, Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Dung Q. Nguyen +1 more 2018-11-20 $2,951,000
10073697 Handling unaligned load operations in a multi-slice computer processor Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more 2018-09-11 $4,894,000
10067763 Handling unaligned load operations in a multi-slice computer processor Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Jentje Leenstra, Dung Q. Nguyen +2 more 2018-09-04 $2,923,000
10042770 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone 2018-08-07 $1,950,000
10037229 Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions Sundeep Chadha, David A. Hrusecky, Hung Q. Le, Elizabeth A. McGlone 2018-07-31 $5,084,000
9940133 Operation of a multi-slice processor implementing simultaneous two-target loads and stores David A. Hrusecky, Jennifer L. Molnar, Jose Angel Paredes, Brian W. Thompto 2018-04-10 $2,135,000
9934033 Operation of a multi-slice processor implementing simultaneous two-target loads and stores David A. Hrusecky, Jennifer L. Molnar, Jose Angel Paredes, Brian W. Thompto 2018-04-03 $2,801,000
9798549 Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction Maarten J. Boersma, David A. Hrusecky, Jennifer L. Molnar, Brian W. Thompto, Albert J. Van Norstrand, Jr. +1 more 2017-10-24 $3,030,000
8489863 Processor including age tracking of issue queue instructions James Wilson Bishop, Mary D. Brown, Jeffrey C. Brownscheidle, Maureen A. Delaney, Jafar Nahidi +2 more 2013-07-16 $5,283,000