Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

Out-of-order processor that avoids deadlock in processing queues by designating a most favored instruction

US Patent 10169046 · Granted Jan 1, 2019

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Gather buffer management for unaligned and gather load operations2025
Hardware-based implementation of secure hash algorithms2025
Systems and methods for dynamic control of a secure mode of operation in a proce2025
Routing instructions in a microprocessor2025
Routing instruction results to a register block of a subdivided register file ba2025
Parallel slice processor having a recirculating load-store queue for fast deallo2024
Parallel slice processor having a recirculating load-store queue for fast deallo2024
Parallel slice processor having a recirculating load-store queue for fast deallo2024
Dispatching multiply and accumulate operations based on accumulator register ind2024
Method and system for on demand control of hardware support for software pointer2024
Assignment of microprocessor register tags at issue time2024
Methods and systems for translating virtual addresses in a virtual memory based 2024