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Processor including age tracking of issue queue instructions |
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2013-07-16 |
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Processor including age tracking of issue queue instructions |
James Wilson Bishop, Mary D. Brown, Jeffrey C. Brownscheidle, Robert A. Cordes, Maureen A. Delaney +2 more |
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Statistical method for hierarchically routing layout utilizing flat route information |
Vikas Agarwal, Yonatan Mittlefehldt |
2013-01-15 |
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Dependency matrix with reduced area and power consumption |
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2012-02-28 |
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Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array |
Sam Gat-Shang Chu, Maureen A. Delaney, Saiful Islam, Dung Q. Nguyen |
2010-02-16 |
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Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor |
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2009-01-13 |
| 7400548 |
Method for providing multiple reads/writes using a 2read/2write register file array |
Sam Gat-Shang Chu, Maureen A. Delaney, Saiful Islam, Dung Q. Nguyen |
2008-07-15 |
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Method and apparatus for dynamic modification of microprocessor instruction group at dispatch |
James Wilson Bishop, Hung Q. Le, Dung Q. Nguyen, Brian W. Thompto |
2007-08-07 |
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Method and circuit for reading and writing an instruction buffer |
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2007-07-10 |
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Apparatus and method for speeding up access time of a large register file with wrap capability |
Sam Gat-Shang Chu, Maureen A. Delaney, Saiful Islam, Dung Q. Nguyen |
2007-07-10 |
