Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9710277 | Processor power management based on class and content of instructions | Venkateswara Madduri, Jonathan Y. Tong | 2017-07-18 |
| 8930678 | Instruction and logic to length decode X86 instructions | Venkateswara Madduri, Jonathan Y. Tong | 2015-01-06 |
| 7783871 | Method to remove stale branch predictions for an instruction prior to execution within a microprocessor | Jonathan D. Combs | 2010-08-24 |
| 7266648 | Cache lock mechanism with speculative allocation | Edwin R. Sutanto, Zhongru Julia Lin, Jeffrey L. Nye | 2007-09-04 |
| 7080241 | Mechanism for self-initiated instruction issuing and method therefor | Hung Q. Le | 2006-07-18 |
| 6986010 | Cache lock mechanism with speculative allocation | Edwin R. Sutanto, Zhongru Julia Lin, Jeffrey L. Nye | 2006-01-10 |
| 6898696 | Method and system for efficiently restoring a processor's execution state following an interrupt caused by an interruptible instruction | Hung Q. Le | 2005-05-24 |
| 6604173 | System for controlling access to external cache memories of differing size | Dwain A. Hicks, George McNeil Lattimore, Peichun Peter Liu | 2003-08-05 |
| 6553480 | System and method for managing the execution of instruction groups having multiple executable instructions | Hung Q. Le | 2003-04-22 |
| 6535973 | Method and system for speculatively issuing instructions | Maureen A. Delaney, Hung Q. Le, Robert G. McDonald, Dung Q. Nguyen, David Wayne Victor | 2003-03-18 |
| 6473850 | System and method for handling instructions occurring after an ISYNC instruction | R. Hay, James Allan Kahle, Hung Q. Le | 2002-10-29 |
| 6324640 | System and method for dispatching groups of instructions using pipelined register renaming | Hung Q. Le | 2001-11-27 |
| 6308260 | Mechanism for self-initiated instruction issuing and method therefor | Hung Q. Le | 2001-10-23 |
| 6098167 | Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution | Hung Q. Le, John Stephen Muhich, Steven Wayne White | 2000-08-01 |
| 6073211 | Method and system for memory updates within a multiprocessor data processing system | Kai Cheng, Kimming So | 2000-06-06 |
| 6070235 | Data processing system and method for capturing history buffer data | Hung Q. Le | 2000-05-30 |
| 6061777 | Apparatus and method for reducing the number of rename registers required in the operation of a processor | Paul J. Jordan, Hung Q. Le, Soummya Mallick | 2000-05-09 |
| 5996085 | Concurrent execution of machine context synchronization operations and non-interruptible instructions | Hung Q. Le | 1999-11-30 |
| 5983341 | Data processing system and method for extending the time for execution of an instruction | Paul J. Jordan, Hung Q. Le | 1999-11-09 |
| 5974524 | Method and apparatus for reducing the number of rename registers in a processor supporting out-of-order execution | Paul J. Jordan, Quan Nguyen, Hung Q. Le | 1999-10-26 |
| 5961636 | Checkpoint table for selective instruction flushing in a speculative execution unit | Jeffrey S. Brooks, Tiberiu Galambos, Christopher H. Olson | 1999-10-05 |
| 5913048 | Dispatching instructions in a processor supporting out-of-order execution | Hung Q. Le, John Stephen Muhich, Steven Wayne White | 1999-06-15 |
| 5897651 | Information handling system including a direct access set associative cache and method for accessing same | Kimming So | 1999-04-27 |
| 5887161 | Issuing instructions in a processor supporting out-of-order execution | Hung Q. Le, John Stephen Muhich, Steven Wayne White | 1999-03-23 |
| 5875326 | Data processing system and method for completing out-of-order instructions | Paul J. Jordan, Hung Q. Le | 1999-02-23 |