Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5870582 | Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched | Hung Q. Le, John Stephen Muhich, Steven Wayne White | 1999-02-09 |
| 5870612 | Method and apparatus for condensed history buffer | Hung Q. Le, John Stephen Muhich, Steven Wayne White | 1999-02-09 |
| 5860014 | Method and apparatus for improved recovery of processor state using history buffer | Hung Q. Le, John Stephen Muhich, Steven Wayne White | 1999-01-12 |
| 5822752 | Method and apparatus for fast parallel determination of queue entries | Michael Kevin Ciraula, Hung Q. Le, John Stephen Muhich | 1998-10-13 |
| 5805906 | Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions | Hung Q. Le, Paul J. Jordan | 1998-09-08 |
| 5774712 | Instruction dispatch unit and method for mapping a sending order of operations to a receiving order | Hung Q. Le | 1998-06-30 |
| 5754885 | Apparatus and method for selecting entries from an array | Tom Tien-Cheng Chiu, Hung Q. Le, Donald George Mikan, Jr. | 1998-05-19 |
| 5694573 | Shared L2 support for inclusion property in split L1 data and instruction caches | Dwain A. Hicks, Kimming So | 1997-12-02 |
| 5692151 | High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address | Dwain A. Hicks, Kimming So | 1997-11-25 |
| 5584013 | Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache | Dwain A. Hicks, Kimming So | 1996-12-10 |
| 5533189 | System and method for error correction code generation | Kimming So | 1996-07-02 |