Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8726292 | System and method for communication in a multithread processor | Jason Leonard | 2014-05-13 |
| 8356158 | Mini-translation lookaside buffer for use in memory translation | Jane Lu | 2013-01-15 |
| 7711906 | System and method for caching | Jin Wang | 2010-05-04 |
| 7627720 | System and method for directional prefetching | Jin Wang | 2009-12-01 |
| 7617380 | System and method for synchronizing translation lookaside buffer access in a multithread processor | Jason Leonard, Gurvinder S. Sareen | 2009-11-10 |
| 7386646 | System and method for interrupt distribution in a multithread processor | Baobinh Truong, Jason Leonard | 2008-06-10 |
| 7167954 | System and method for caching | Jin Wang | 2007-01-23 |
| 7111127 | System for supporting unlimited consecutive data stores into a cache memory | Chia-Cheng Choung, Baobinh Truong, Yook-Khai Cheok | 2006-09-19 |
| 6963613 | Method of communicating between modules in a decoding system | Alexander G. MacInnis, Vivian Hsiun, Sheng Zhong, Xiaodong Xie, Jose R. Alvarez | 2005-11-08 |
| 6957306 | System and method for controlling prefetching | Chengfuh Jeffrey Tang, Eric Tsang | 2005-10-18 |
| 6944746 | RISC processor supporting one or more uninterruptible co-processors | — | 2005-09-13 |
| 6931494 | System and method for directional prefetching | Jin Wang | 2005-08-16 |
| 6073211 | Method and system for memory updates within a multiprocessor data processing system | Kai Cheng, Hoichi Cheong | 2000-06-06 |
| 5897651 | Information handling system including a direct access set associative cache and method for accessing same | Hoichi Cheong | 1999-04-27 |
| 5699538 | Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor | Hung Q. Le, Bao-Binh Truong | 1997-12-16 |
| 5694573 | Shared L2 support for inclusion property in split L1 data and instruction caches | Hoichi Cheong, Dwain A. Hicks | 1997-12-02 |
| 5692151 | High performance/low cost access hazard detection in pipelined cache controller using comparators with a width shorter than and independent of total width of memory address | Hoichi Cheong, Dwain A. Hicks | 1997-11-25 |
| 5655103 | System and method for handling stale data in a multiprocessor system | Kai Cheng, Jin Wang | 1997-08-05 |
| 5584013 | Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache | Hoichi Cheong, Dwain A. Hicks | 1996-12-10 |
| 5581734 | Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity | Michael Thomas Dibrino, Dwain A. Hicks, George McNeil Lattimore, Hanaa Youssef | 1996-12-03 |
| 5553253 | Correlation-based branch prediction in digital computers | Shien-Tai Pan | 1996-09-03 |
| 5533189 | System and method for error correction code generation | Hoichi Cheong | 1996-07-02 |
| 5530832 | System and method for practicing essential inclusion in a multiprocessor and cache hierarchy | Wen-Hann Wang | 1996-06-25 |
| 5133061 | Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses | Evelyn A. Melton, Vern A. Norton, Gregory F. Pfister | 1992-07-21 |
| 5048018 | Debugging parallel programs by serialization | David H. Bernstein | 1991-09-10 |