| 5133061 |
Mechanism for improving the randomization of cache accesses utilizing abit-matrix multiplication permutation of cache addresses |
Evelyn A. Melton, Gregory F. Pfister, Kimming So |
1992-07-21 |
| 5125096 |
System for implementing to a packet switch protocol for a multinode data communications network utilizing separate data and control paths |
William C. Brantley, Wayne S. Groh, Rory Jackson |
1992-06-23 |
| 5111389 |
Aperiodic mapping system using power-of-two stride access to interleaved devices |
Keven P. McAuliffe, Evelyn A. Melton, Gregoty F. Pfister, Scott P. Wakefield |
1992-05-05 |
| 4980822 |
Multiprocessing system having nodes containing a processor and an associated memory module with dynamically allocated local/global storage in the memory modules |
William C. Brantley, Kevin P. McAuliffe, Gregory F. Pfister, Joseph M. Weiss |
1990-12-25 |
| 4969088 |
Hardware mechanism for automatically detecting hot-spot references and diverting same from memory traffic in a multiprocessor computer system |
Kevin P. McAuliffe, Gregory F. Pfister, Bharat D. Rathi |
1990-11-06 |
| 4885680 |
Method and apparatus for efficiently handling temporarily cacheable data |
John Anthony, William C. Brantley, Kevin P. McAuliffe, Gregory F. Pfister |
1989-12-05 |
| 4754394 |
Multiprocessing system having dynamically allocated local/global storage and including interleaving transformation circuit for transforming real addresses to corresponding absolute address of the storage |
William C. Brantley, Kevin P. McAuliffe, Gregory F. Pfister, Joseph M. Weiss |
1988-06-28 |
