WW

Wen-Hann Wang

IN Intel: 18 patents #2,286 of 30,777Top 8%
IBM: 1 patents #44,794 of 70,183Top 65%
Overall (All Time): #240,265 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8745306 Scalable distributed memory and I/O multiprocessor system Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Kai Cheng, Richard H. Hofsheier +1 more 2014-06-03
8255605 Scalable distributed memory and I/O multiprocessor system Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Kai Cheng, Richard H. Hofsheier +1 more 2012-08-28
7930464 Scalable memory and I/O multiprocessor systems Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Kai Cheng, Richard H. Hofsheier +1 more 2011-04-19
7603508 Scalable distributed memory and I/O multiprocessor systems and associated methods Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Kai Cheng, Richard H. Hofsheier +1 more 2009-10-13
7343442 Scalable distributed memory and I/O multiprocessor systems and associated methods Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Kai Cheng, Richard H. Hofsheier +1 more 2008-03-11
7076613 Cache line pre-load and pre-own based on cache coherence speculation Jih-Kwon Peir, Steve Yu Zhang, Scott H. Robinson, Konrad K. Lai 2006-07-11
7058750 Scalable distributed memory and I/O multiprocessor system Linda J. Rankin, Paul R. Pierce, Gregory E. Dermer, Kai Cheng, Richard H. Hofsheier +1 more 2006-06-06
6725341 Cache line pre-load and pre-own based on cache coherence speculation Jih-Kwon Peir, Steve Yu Zhang, Scott H. Robinson, Konrad K. Lai 2004-04-20
6006299 Apparatus and method for caching lock conditions in a multi-processor system Konrad K. Lai, Gurbir Singh, Mandar Joshi, Nitin V. Sarangdhar, Matthew A. Fisch 1999-12-21
5956746 Computer system having tag information in a processor and cache memory 1999-09-21
5829038 Backward inquiry to lower level caches prior to the eviction of a modified line from a higher level cache in a microprocessor hierarchical cache structure Quinn W. Merrell 1998-10-27
5809524 Method and apparatus for cache memory replacement line identification Gurbir Singh, Michael W. Rhodehamel, John M. Bauer, Nitin V. Sarangdhar 1998-09-15
5715428 Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system Konrad K. Lai, Gurbir Singh, Michael W. Rhodehamel, Nitin V. Sarangdhar, John M. Bauer +2 more 1998-02-03
5701503 Method and apparatus for transferring information between a processor and a memory system Gurbir Singh, Michael W. Rhodehamel, John M. Bauer, Nitin V. Sarangdhar 1997-12-23
5642494 Cache memory with reduced request-blocking John M. Bauer 1997-06-24
5619673 Virtual access cache protection bits handling method and apparatus 1997-04-08
5551005 Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches Nitin V. Sarangdhar, Matthew A. Fisch 1996-08-27
5548742 Method and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memory Konrad K. Lai 1996-08-20
5530832 System and method for practicing essential inclusion in a multiprocessor and cache hierarchy Kimming So 1996-06-25