| 7802083 |
Utilization based installation on a computing system |
Nagasubramanian Gurumoorthy, Arvind Kumar |
2010-09-21 |
$10,255,000 |
| RE38388 |
Method and apparatus for performing deferred transactions |
Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Peter D. MacWilliams, Stephen S. Pawlowski |
2004-01-13 |
|
| 6114887 |
Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme |
Chakrapani Pathikonda, Matthew A. Fisch |
2000-09-05 |
$299,695,000 |
| 6061599 |
Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair |
Nitin V. Sarangdhar, Chakrapani Pathikonda |
2000-05-09 |
$498,077,000 |
| 6055656 |
Control register bus access through a standardized test access port |
James A. Wilson, Anthony C. Miller, Adrian Carbine, Derek B. Feltham, Sumeet Agrawal |
2000-04-25 |
$208,912,000 |
| 6009477 |
Bus agent providing dynamic pipeline depth control |
Nitin V. Sarangdhar, Matthew A. Fisch |
1999-12-28 |
$186,062,000 |
| 5948088 |
Bus system providing dynamic control of pipeline depth for a multi-agent computer |
Nitin V. Sarangdhar, Matthew A. Fisch |
1999-09-07 |
$115,425,000 |
| 5909699 |
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency |
Nitin V. Sarangdhar, Amit Merchant, Matthew A. Fisch, James M. Brayton |
1999-06-01 |
$142,810,000 |
| 5901297 |
Initialization mechanism for symmetric arbitration agents |
Matthew A. Fisch, Nitin V. Sarangdhar |
1999-05-04 |
$187,330,000 |
| 5896513 |
Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols |
Matthew A. Fisch, James E. Jacobson, Jr. |
1999-04-20 |
$155,334,000 |
| 5845107 |
Signaling protocol conversion between a processor and a high-performance system bus |
Matthew A. Fisch, James E. Jacobson, Jr. |
1998-12-01 |
$77,437,000 |
| 5832534 |
Method and apparatus for maintaining cache coherency using a single controller for multiple cache memories |
Gurbir Singh, Konrad K. Lai |
1998-11-03 |
$60,287,000 |
| 5809524 |
Method and apparatus for cache memory replacement line identification |
Gurbir Singh, Wen-Hann Wang, John M. Bauer, Nitin V. Sarangdhar |
1998-09-15 |
$52,435,000 |
| 5802132 |
Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme |
Chakrapani Pathikonda, Matthew A. Fisch |
1998-09-01 |
$44,085,000 |
| 5797026 |
Method and apparatus for self-snooping a bus during a boundary transaction |
Nitin V. Sarangdhar, Amit Merchant, Matthew A. Fisch, James M. Brayton |
1998-08-18 |
$76,383,000 |
| 5796977 |
Highly pipelined bus architecture |
Nitin V. Sarangdhar, Gurbir Singh, Konrad K. Lai, Stephen S. Pawlowski, Peter D. MacWilliams |
1998-08-18 |
$76,383,000 |
| 5784579 |
Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth |
Stephen S. Pawlowski, Nitin V. Sarangdhar, Matthew A. Fisch, Peter D. MacWilliams |
1998-07-21 |
$100,261,000 |
| 5778441 |
Method and apparatus for accessing split lock variables in a computer system |
Nitin V. Sarangdhar, Matthew A. Fisch |
1998-07-07 |
$55,069,000 |
| 5764934 |
Processor subsystem for use with a universal computer architecture |
Matthew A. Fisch, James E. Jacobson, Jr. |
1998-06-09 |
$57,213,000 |
| 5761449 |
Bus system providing dynamic control of pipeline depth for a multi-agent computer |
Nitin V. Sarangdhar, Matthew A. Fisch |
1998-06-02 |
$54,938,000 |
| 5754833 |
Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio |
Gurbir Singh |
1998-05-19 |
$58,580,000 |
| 5715428 |
Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system |
Wen-Hann Wang, Konrad K. Lai, Gurbir Singh, Nitin V. Sarangdhar, John M. Bauer +2 more |
1998-02-03 |
$122,866,000 |
| 5701503 |
Method and apparatus for transferring information between a processor and a memory system |
Gurbir Singh, Wen-Hann Wang, John M. Bauer, Nitin V. Sarangdhar |
1997-12-23 |
$56,356,000 |
| 5682516 |
Computer system that maintains system wide cache coherency during deferred communication transactions |
Nitin V. Sarangdhar, Wen-Han Wang, James M. Brayton, Amit Merchant, Matthew A. Fisch |
1997-10-28 |
$146,510,000 |
| 5636374 |
Method and apparatus for performing operations based upon the addresses of microinstructions |
Scott Dion Rodgers, Keshavan Tiruvallur, Kris G. Konigsfeld, Andrew F. Glew, Haitham Akkary +2 more |
1997-06-03 |
$137,246,000 |
