Chakrapani Pathikonda has been granted 10 US patents while listed as an inventor at Intel . The first was granted in 1998 and the most recent in July 2001. Chakrapani Pathikonda ranks #481,000 of 4,157,543 US inventors in our database (top 11.6%). Patent records list Chakrapani Pathikonda in Beaverton, OR, US.
Patents per Year Patents granted per year, 1998 to 2001 Bar chart with a peak of 4 patents in 1998. peak 4 1998: 4 patents 1998 1999: 1 patents 1999 2000: 3 patents 2000 2001: 2 patents 2001
Issued Patents All Time
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Showing 1–10 of 10 patents
Patent # Title Co-Inventors Date Approx Value ⓘ
6268749 Core clock correction in a 2/n mode clocking scheme Matthew A. Fisch , Javed S. Barkatullah 2001-07-31
$265,780,000
6208180 Core clock correction in a 2/N mode clocking scheme Matthew A. Fisch , Javed S. Barkatullah 2001-03-27
$117,605,000
6114887 Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme Matthew A. Fisch , Michael W. Rhodehamel 2000-09-05
$299,695,000
6104219 Method and apparatus for generating 2/N mode bus clock signals Javed S. Barkatullah 2000-08-15
$313,766,000
6061599 Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair Michael W. Rhodehamel , Nitin V. Sarangdhar 2000-05-09
$498,077,000
5862373 Pad cells for a 2/N mode clocking scheme Jeff Wight 1999-01-19
$152,384,000
5834956 Core clock correction in a 2/N mode clocking scheme Matthew A. Fisch , Javed S. Barkatullah 1998-11-10
$74,050,000
5826067 Method and apparatus for preventing logic glitches in a 2/n clocking scheme Matthew A. Fisch 1998-10-20
$74,450,000
5821784 Method and apparatus for generating 2/N mode bus clock signals Javed S. Barkatullah 1998-10-13
$57,272,000
5802132 Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme Matthew A. Fisch , Michael W. Rhodehamel 1998-09-01
$44,085,000
