Issued Patents All Time
Showing 26–31 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5623628 | Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue | James M. Brayton, Nitin V. Sarangdhar, Glenn J. Hinton | 1997-04-22 |
| 5615343 | Method and apparatus for performing deferred transactions | Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Peter D. MacWilliams, Stephen S. Pawlowski | 1997-03-25 |
| 5581782 | Computer system with distributed bus arbitration scheme for symmetric and priority agents | Nitin V. Sarangdhar, Konrad K. Lai, Gurbir Singh, Matthew A. Fisch | 1996-12-03 |
| 5572702 | Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency | Nitin V. Sarangdhar, Amit Merchant, Matthew A. Fisch, James M. Brayton | 1996-11-05 |
| 5548733 | Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system | Nitin V. Sarangdhar, Matthew A. Fisch | 1996-08-20 |
| 5515516 | Initialization mechanism for symmetric arbitration agents | Matthew A. Fisch, Nitin V. Sarangdhar | 1996-05-07 |