Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5909699 | Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency | Nitin V. Sarangdhar, Michael W. Rhodehamel, Amit Merchant, Matthew A. Fisch | 1999-06-01 |
| 5797026 | Method and apparatus for self-snooping a bus during a boundary transaction | Michael W. Rhodehamel, Nitin V. Sarangdhar, Amit Merchant, Matthew A. Fisch | 1998-08-18 |
| 5682516 | Computer system that maintains system wide cache coherency during deferred communication transactions | Nitin V. Sarangdhar, Wen-Han Wang, Michael W. Rhodehamel, Amit Merchant, Matthew A. Fisch | 1997-10-28 |
| 5623628 | Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue | Michael W. Rhodehamel, Nitin V. Sarangdhar, Glenn J. Hinton | 1997-04-22 |
| 5572702 | Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency | Nitin V. Sarangdhar, Michael W. Rhodehamel, Amit Merchant, Matthew A. Fisch | 1996-11-05 |
| 5535345 | Method and apparatus for sequencing misaligned external bus transactions in which the order of completion of corresponding split transaction requests is guaranteed | Matthew A. Fisch, Ajay Malhotra | 1996-07-09 |