Issued Patents All Time
Showing 25 most recent of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6412051 | System and method for controlling a memory array in an information handling system | Brian R. Konigsburg, George McNeil Lattimore | 2002-06-25 |
| 6389585 | Method and system for building a multiprocessor data processing system | Robert P. Masleid, Amy May Tuvell | 2002-05-14 |
| 6266767 | Apparatus and method for facilitating out-of-order execution of load instructions | Kurt A. Feiste, Steven Wayne White | 2001-07-24 |
| 6167500 | Mechanism for queuing store data and method therefor | Kurt A. Feiste, Steven Wayne White | 2000-12-26 |
| 6098167 | Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution | Hoichi Cheong, Hung Q. Le, Steven Wayne White | 2000-08-01 |
| 6079002 | Dynamic expansion of execution pipeline stages | Larry Edward Thatcher, Steven Wayne White, Troy N. Hicks | 2000-06-20 |
| 6070238 | Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction | Kurt A. Feiste, Steven Wayne White | 2000-05-30 |
| 6055557 | Adder circuit and method therefor | John Andrew Beck, James E. Dunning | 2000-04-25 |
| 6021512 | Data processing system having memory sub-array redundancy and method therefor | George McNeil Lattimore, Robert P. Masleid | 2000-02-01 |
| 6021467 | Apparatus and method for processing multiple cache misses to a single cache line | Brian R. Konigsburg, Larry Edward Thatcher, Steven Wayne White | 2000-02-01 |
| 6021485 | Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching | Kurt A. Feiste, Larry Edward Thatcher, Steven Wayne White | 2000-02-01 |
| 6014047 | Method and apparatus for phase rotation in a phase locked loop | Daniel M. Dreps, Robert P. Masleid | 2000-01-11 |
| 6002285 | Circuitry and method for latching information | Quan Nguyen | 1999-12-14 |
| 5949262 | Method and apparatus for coupled phase locked loops | Daniel M. Dreps, Robert P. Masleid | 1999-09-07 |
| 5931957 | Support for out-of-order execution of loads and stores in a processor | Brian R. Konigsburg, Larry Edward Thatcher, Steven Wayne White | 1999-08-03 |
| 5918044 | Apparatus and method for instruction fetching using a multi-port instruction cache directory | David S. Levitan | 1999-06-29 |
| 5913048 | Dispatching instructions in a processor supporting out-of-order execution | Hoichi Cheong, Hung Q. Le, Steven Wayne White | 1999-06-15 |
| 5887161 | Issuing instructions in a processor supporting out-of-order execution | Hoichi Cheong, Hung Q. Le, Steven Wayne White | 1999-03-23 |
| 5872950 | Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages | David S. Levitan | 1999-02-16 |
| 5870582 | Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched | Hoichi Cheong, Hung Q. Le, Steven Wayne White | 1999-02-09 |
| 5870612 | Method and apparatus for condensed history buffer | Hoichi Cheong, Hung Q. Le, Steven Wayne White | 1999-02-09 |
| 5870592 | Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator | Daniel M. Dreps, Robert P. Masleid | 1999-02-09 |
| 5864341 | Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding | Troy N. Hicks, Hung Q. Le, Steven Wayne White | 1999-01-26 |
| 5860014 | Method and apparatus for improved recovery of processor state using history buffer | Hoichi Cheong, Hung Q. Le, Steven Wayne White | 1999-01-12 |
| 5848283 | Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization | Charles Roberts Moore, Brian James Vicknair | 1998-12-08 |