| 6938148 |
Managing load and store operations using a storage management unit with data flow architecture |
Ravi Nair, Wolfram Sauer |
2005-08-30 |
| 6766442 |
Processor and method that predict condition register-dependent conditional branch instructions utilizing a potentially stale condition register value |
James Allan Kahle |
2004-07-20 |
| 6748519 |
Method and apparatus for utilizing renamed registers based upon a functional or defective operational status of the register |
— |
2004-06-08 |
| 6728866 |
Partitioned issue queue and allocation strategy |
James Allan Kahle |
2004-04-27 |
| 6725354 |
Shared execution unit in a dual core processor |
James Allan Kahle |
2004-04-20 |
| 6678820 |
Processor and method for separately predicting conditional branches dependent on lock acquisition |
James Allan Kahle |
2004-01-13 |
| 6662294 |
Converting short branches to predicated instructions |
James Allan Kahle |
2003-12-09 |
| 6658555 |
Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline |
James Allan Kahle, Hung Q. Le, David Shippy, Larry Edward Thatcher |
2003-12-02 |
| 6658558 |
Branch prediction circuit selector with instruction context related condition type determining |
James Allan Kahle |
2003-12-02 |
| 6654869 |
Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling |
James Allan Kahle, Hung Q. Le |
2003-11-25 |
| 6625746 |
Microprocessor instruction buffer redundancy scheme |
— |
2003-09-23 |
| 6609190 |
Microprocessor with primary and secondary issue queue |
James Allan Kahle |
2003-08-19 |
| 5848283 |
Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization |
John Stephen Muhich, Brian James Vicknair |
1998-12-08 |
| 5793986 |
Method and system for enhanced efficiency of data transfers from memory to multiple processors in a data processing system |
Michael S. Allen, Robert J. Reese |
1998-08-11 |
| 5724565 |
Method and system for processing first and second sets of instructions by first and second types of processing systems |
Pradeep Kumar Dubey, Terence M. Potter |
1998-03-03 |
| 5706464 |
Method and system for achieving atomic memory references in a multilevel cache data processing system |
John Stephen Muhich, Robert J. Reese |
1998-01-06 |
| 5692218 |
System for transferring data between input/output devices having separate address spaces in accordance with initializing information in address packages |
Michael S. Allen, Michael Garcia, Robert J. Reese |
1997-11-25 |
| 5611058 |
System and method for transferring information between multiple buses |
John Stephen Muhich, Robert J. Reese |
1997-03-11 |
| 5603057 |
System for initiating data transfer between input/output devices having separate address spaces in accordance with initializing information in two address packages |
Michael S. Allen, Yoanna Baumgartner, Michael Garcia, Robert J. Reese |
1997-02-11 |
| 5500950 |
Data processor with speculative data transfer and address-free retry |
Michael Becker, John Stephen Muhich, Robert J. Reese |
1996-03-19 |
| 5442766 |
Method and system for distributed instruction address translation in a multiscalar data processing system |
Tan V. Chu, John Stephen Muhich, Terence M. Potter |
1995-08-15 |
| 5437017 |
Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system |
John Stephen Muhich |
1995-07-25 |
