Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5822752 | Method and apparatus for fast parallel determination of queue entries | Hoichi Cheong, Michael Kevin Ciraula, Hung Q. Le | 1998-10-13 |
| 5812418 | Cache sub-array method and apparatus for use in microprocessor integrated circuits | George McNeil Lattimore, Robert P. Masleid | 1998-09-22 |
| 5802571 | Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory | Brian R. Konigsburg, Steven Wayne White | 1998-09-01 |
| 5796998 | Apparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling system | David S. Levitan, Adam R. Talcott, Steven Wayne White | 1998-08-18 |
| 5784604 | Method and system for reduced run-time delay during conditional branch execution in pipelined processor systems utilizing selectively delayed sequential instruction purging | Terrence Matthew Potter, Steven Wayne White | 1998-07-21 |
| 5758120 | Method and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bits | James Allan Kahle, Richard R. Oehler, Edward John Silha | 1998-05-26 |
| 5742784 | System for reordering of instructions before placement into cache to reduce dispatch latency | Terence M. Potter, Christopher H. Olson, Timothy A. Elliott | 1998-04-21 |
| 5729501 | High Speed SRAM with or-gate sense | Larry B. Phillips, Robert P. Masleid | 1998-03-17 |
| 5706464 | Method and system for achieving atomic memory references in a multilevel cache data processing system | Charles Roberts Moore, Robert J. Reese | 1998-01-06 |
| 5689198 | Circuitry and method for gating information | Lawrence Joseph Merkel | 1997-11-18 |
| 5668525 | Comparator circuit using two bit to four bit encoder | Tom Tien-Cheng Chiu, Donald George Mikan, Jr. | 1997-09-16 |
| 5668761 | Fast read domino SRAM | Robert P. Masleid, Larry B. Phillips | 1997-09-16 |
| 5640518 | Addition of pre-last transfer acknowledge signal to bus interface to eliminate data bus turnaround on consecutive read and write tenures and to allow burst transfers of unknown length | Ronald Xavier Arroyo, Charles Wright, Lawrence Joseph Merkel | 1997-06-17 |
| 5623450 | Conditional recharge for dynamic logic | Larry B. Phillips, Robert P. Masleid | 1997-04-22 |
| 5615160 | Minimal recharge overhead circuit for domino SRAM structures | Larry B. Phillips, Robert P. Masleid | 1997-03-25 |
| 5611058 | System and method for transferring information between multiple buses | Charles Roberts Moore, Robert J. Reese | 1997-03-11 |
| 5532947 | Combined decoder/adder circuit which provides improved access speed to a cache | Terence M. Potter | 1996-07-02 |
| 5500950 | Data processor with speculative data transfer and address-free retry | Michael Becker, Charles Roberts Moore, Robert J. Reese | 1996-03-19 |
| 5463739 | Apparatus for vetoing reallocation requests during a data transfer based on data bus latency and the number of received reallocation requests below a threshold | Virgil A. Albaugh, Edward John Silha, Michael Terrell Vanover | 1995-10-31 |
| 5442766 | Method and system for distributed instruction address translation in a multiscalar data processing system | Tan V. Chu, Charles Roberts Moore, Terence M. Potter | 1995-08-15 |
| 5437017 | Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system | Charles Roberts Moore | 1995-07-25 |
| 4763251 | Merge and copy bit block transfer implementation | Arthur A. Kauffman, Jr. | 1988-08-09 |
| 4742350 | Software managed video synchronization generation | Michael A. Ko | 1988-05-03 |
| 4740927 | Bit addressable multidimensional array | David Cureton Baker | 1988-04-26 |
| 4706074 | Cursor circuit for a dual port memory | Joseph S. Thornley | 1987-11-10 |