Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8826241 | Instruction sampling in a multi-threaded processor | Mario I. Wolczko | 2014-09-02 |
| 8762951 | Apparatus and method for profiling system events in a fine grain multi-threaded multi-core processor | Nicolai Kosche, James Laudon, Sanjay Patel, Farnad Sajjadian | 2014-06-24 |
| 7827383 | Efficient on-chip accelerator interfaces to reduce software overhead | Lawrence Spracklen, Santosh Abraham | 2010-11-02 |
| 7809895 | Low overhead access to shared on-chip hardware accelerator with memory-based interfaces | Lawrence Spracklen, Santosh Abraham, Sothea Soun, Sanjay Patel, Farnad Sajjadian | 2010-10-05 |
| 7707554 | Associating data source information with runtime events | Nicolai Kosche, Robert E. Cypher, Mario I. Wolczko, John P. Petry | 2010-04-27 |
| 7096390 | Sampling mechanism including instruction filtering | Mario I. Wolczko | 2006-08-22 |
| 6948055 | Accuracy of multiple branch prediction schemes | — | 2005-09-20 |
| 6934830 | Method and apparatus for reducing register file access times in pipelined processors | Sudarshan Kadambi, Wayne Yamamoto | 2005-08-23 |
| 6738897 | Incorporating local branch history when predicting multiple conditional branch outcomes | — | 2004-05-18 |
| 6615343 | Mechanism for delivering precise exceptions in an out-of-order processor with speculative execution | Daniel L. Liebholz, Sanjay Patel, Richard H. Larson | 2003-09-02 |
| 6510511 | Methods and apparatus for branch prediction using hybrid history with index sharing | — | 2003-01-21 |
| 6330662 | Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures | Sanjay Patel, Rajasekhar Cherabuddi | 2001-12-11 |
| 6289441 | Method and apparatus for performing multiple branch predictions per cycle | Ramesh Panwar, Rajasekhar Cherabuddi, Sanjay Patel | 2001-09-11 |
| 6272623 | Methods and apparatus for branch prediction using hybrid history with index sharing | — | 2001-08-07 |
| 6256729 | Method and apparatus for resolving multiple branches | Rajasekhar Cherabuddi, Sanjay Patel, Ramesh Panwar | 2001-07-03 |
| 6256709 | Method for storing data in two-way set associative odd and even banks of a cache memory | Sanjay Patel, Rajasekhar Cherabuddi, Ramesh Panwar | 2001-07-03 |
| 6134654 | Bi-level branch target prediction scheme with fetch address prediction | Sanjay Patel, Rajasekhar Cherabuddi | 2000-10-17 |
| 6115810 | Bi-level branch target prediction scheme with mux select prediction | Sanjay Patel, Rajasekhar Cherabuddi | 2000-09-05 |
| 5964869 | Instruction fetch mechanism with simultaneous prediction of control-flow instructions | Ramesh Panwar | 1999-10-12 |
| 5941985 | Branch instruction prediction method | Ramesh Panwar | 1999-08-24 |
| 5938761 | Method and apparatus for branch target prediction | Sanjay Patel, Rajasekhar Cherabuddi | 1999-08-17 |
| 5935238 | Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles | Ramesh Panwar | 1999-08-10 |
| 5875325 | Processor having reduced branch history table size through global branch history compression and method of branch prediction utilizing compressed global branch history | — | 1999-02-23 |
| 5857098 | Branch instruction prediction apparatus | Ramesh Panwar | 1999-01-05 |
| 5854761 | Cache memory array which stores two-way set associative data | Sanjay Patel, Rajasekhar Cherabuddi, Ramesh Panwar | 1998-12-29 |