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Store handling in a processor |
Ramesh Gunna, Po-Yung Chang |
2014-11-18 |
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Converting victim writeback to a fill |
Ramesh Gunna |
2013-01-29 |
| 8316188 |
Data prefetch unit utilizing duplicate cache tags |
Puneet Kumar, Po-Yung Chang |
2012-11-20 |
| 8301843 |
Data cache block zero implementation |
Ramesh Gunna, Peter J. Bannon |
2012-10-30 |
| 8239638 |
Store handling in a processor |
Ramesh Gunna, Po-Yung Chang |
2012-08-07 |
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Ramesh Gunna |
2012-03-06 |
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Puneet Kumar, Po-Yung Chang |
2011-08-09 |
| 7984274 |
Partial load/store forward prediction |
Po-Yung Chang, Eric Hao |
2011-07-19 |
| 7836262 |
Converting victim writeback to a fill |
Ramesh Gunna |
2010-11-16 |
| 7779208 |
Prefetch unit |
Puneet Kumar, Po-Yung Chang |
2010-08-17 |
| 7707361 |
Data cache block zero implementation |
Ramesh Gunna, Peter J. Bannon |
2010-04-27 |
| 7568087 |
Partial load/store forward prediction |
Po-Yung Chang, Eric Hao |
2009-07-28 |
| 7493451 |
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Puneet Kumar, Po-Yung Chang |
2009-02-17 |
| 7487296 |
Multi-stride prefetcher with a recurring prefetch table |
Sorin Iacobovici, Yuan C. Chou |
2009-02-03 |
| 7376817 |
Partial load/store forward prediction |
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2008-05-20 |
| 7237096 |
Storing results of producer instructions to facilitate consumer instruction dependency tracking |
Julian Prabhu, Atul Kalambur, Daniel L. Liebholz, Julie M. Staraitis |
2007-06-26 |
| 7076640 |
Processor that eliminates mis-steering instruction fetch resulting from incorrect resolution of mis-speculated branch instructions |
— |
2006-07-11 |
| 7055021 |
Out-of-order processor that reduces mis-speculation using a replay scoreboard |
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2006-05-30 |
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Method and apparatus for avoiding cache pollution due to speculative memory load operations in a microprocessor |
Vijay Balakrishnan |
2006-03-07 |
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Method and apparatus for predicting hot spots in cache memories |
Vijay Balakrishnan, Wayne Yamamoto |
2005-12-13 |
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Method and apparatus for reducing the effects of hot spots in cache memories |
Vijay Balakrishnan, Wayne Yamamoto |
2005-09-20 |
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Method and apparatus for reducing register file access times in pipelined processors |
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2005-08-23 |
