Issued Patents All Time
Showing 1–25 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11838397 | Systems and methods for synchronization of processing elements | — | 2023-12-05 |
| 11275712 | SIMD controller and SIMD predication scheme | Paul Kenton Tschirhart | 2022-03-15 |
| 10795683 | Predicting indirect branches using problem branch filtering and pattern cache | Richard J. Eickemeyer, Tejas Karkhanis, David S. Levitan, Douglas R. G. Logan, Mauricio J. Serrano | 2020-10-06 |
| 10685002 | Radix sort acceleration using custom asic | Rajesh Bordawekar, Daniel Brand, Minsik Cho, Ruchir Puri | 2020-06-16 |
| 10545739 | LLVM-based system C compiler for architecture synthesis | Minsik Cho, Indira Nair, Haoxing Ren, Jeonghee Shin | 2020-01-28 |
| 9953044 | Radix sort acceleration using custom ASIC | Rajesh Bordawekar, Daniel Brand, Minsik Cho, Ruchir Puri | 2018-04-24 |
| 9946512 | Adaptive radix external in-place radix sort | Minsik Cho, Vincent Kulandaisamy, Ruchir Puri | 2018-04-17 |
| 9928261 | Radix sort acceleration using custom ASIC | Rajesh Bordawekar, Daniel Brand, Minsik Cho, Ruchir Puri | 2018-03-27 |
| 9858373 | In-cycle resource sharing for high-level synthesis of microprocessors | Minsik Cho, Jeonghee Shin | 2018-01-02 |
| 9779803 | Memory circuit with write-bypass portion | Paul Keaton Tschirhart | 2017-10-03 |
| 9741419 | Memory system with a content addressable superconducting memory | William Robert Reohr | 2017-08-22 |
| 9715411 | Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing system | Richard W. Doing, David S. Levitan, Kevin N. Magill | 2017-07-25 |
| 9665674 | Automating a microarchitecture design exploration environment | Minsik Cho, Indira Nair, Haoxing Ren, Jeonghee Shin | 2017-05-30 |
| 9613699 | Memory system with a content addressable superconducting memory | William Robert Reohr | 2017-04-04 |
| 9524166 | Tracking long GHV in high performance out-of-order superscalar processors | Richard J. Eickemeyer, Tejas Karkhanis, David S. Levitan, Douglas R. G. Logan, Jose E. Moreira +1 more | 2016-12-20 |
| 9507891 | Automating a microarchitecture design exploration environment | Minsik Cho, Indira Nair, Haoxing Ren, Jeonghee Shin | 2016-11-29 |
| 9495170 | Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall | Venkat R. Indukuru, Alexander Erik Mericas, Benjamin W. Stolt | 2016-11-15 |
| 9442736 | Techniques for selecting a predicted indirect branch address from global and local caches | Richard J. Eickemeyer, Tejas Karkhanis, David S. Levitan, Douglas R. G. Logan | 2016-09-13 |
| 9405866 | Automating a microarchitecture design exploration environment | Minsik Cho, Indira Nair, Haoxing Ren, Jeonghee Shin | 2016-08-02 |
| 9170920 | Identifying and tagging breakpoint instructions for facilitation of software debug | David S. Levitan | 2015-10-27 |
| 9081895 | Identifying and tagging breakpoint instructions for facilitation of software debug | David S. Levitan | 2015-07-14 |
| 9069563 | Reducing store-hit-loads in an out-of-order processor | David S. Levitan, Brian R. Mestan, David Mui | 2015-06-30 |
| 8943301 | Storing branch information in an address table of a processor | David S. Levitan, Wolfram Sauer, Samuel Thomas | 2015-01-27 |
| 8943299 | Operating a stack of information in an information handling system | Kattamuri Ekanadham, David S. Levitan, Jose E. Moreira, David Mui, Il Park | 2015-01-27 |
| 8635436 | Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall | Venkat R. Indukuru, Alexander Erik Mericas, Benjamin W. Stolt | 2014-01-21 |