Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7984280 | Storing branch information in an address table of a processor | David S. Levitan, Wolfram Sauer, Samuel Thomas | 2011-07-19 |
| 7487334 | Branch encoding before instruction cache write | Hung Q. Le, David S. Levitan, John W. Ward, III | 2009-02-03 |
| 7475223 | Fetch-side instruction dispatch group formation | Hung Q. Le, David S. Levitan, John W. Ward, III | 2009-01-06 |
| 7426631 | Methods and systems for storing branch information in an address table of a processor | David S. Levitan, Wolfram Sauer, Samuel Thomas | 2008-09-16 |
| 7237094 | Instruction group formation and mechanism for SMT dispatch | Brian W. Curran, Hung Q. Le, David Arnold Luick, Dung Q. Nguyen | 2007-06-26 |
| 6662360 | Method and system for software control of hardware branch prediction mechanism in a data processor | Robert William Hay, James Allan Kahle, David S. Levitan, Balaram Sinharoy | 2003-12-09 |
| 6622236 | Microprocessor instruction fetch unit for processing instruction groups having multiple branch instructions | Kevin Arthur Chiarot, Dave S. Levitan | 2003-09-16 |
| 6484230 | Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction | Alexander Edward Okpisz, Thomas A. Petersen, Bruce Joseph Ronchetti | 2002-11-19 |
| 6412051 | System and method for controlling a memory array in an information handling system | George McNeil Lattimore, John Stephen Muhich | 2002-06-25 |
| 6385719 | Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor | John Edward Derrick, Lee Evan Eisen, David S. Levitan | 2002-05-07 |
| 6304959 | Simplified method to generate BTAGs in a decode unit of a processing system | John Edward Derrick, David S. Levitan | 2001-10-16 |
| 6286094 | Method and system for optimizing the fetching of dispatch groups in a superscalar processor | John Edward Derrick, Lee Evan Eisen, Hung Q. Le | 2001-09-04 |
| 6279105 | Pipelined two-cycle branch target address cache | David S. Levitan | 2001-08-21 |
| 6021467 | Apparatus and method for processing multiple cache misses to a single cache line | John Stephen Muhich, Larry Edward Thatcher, Steven Wayne White | 2000-02-01 |
| 5931957 | Support for out-of-order execution of loads and stores in a processor | John Stephen Muhich, Larry Edward Thatcher, Steven Wayne White | 1999-08-03 |
| 5805849 | Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions | Paul J. Jordan, Hung Q. Le, Steven Wayne White | 1998-09-08 |
| 5802571 | Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory | John Stephen Muhich, Steven Wayne White | 1998-09-01 |
| 5784391 | Distributed memory system with ECC and method of operation | — | 1998-07-21 |