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Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions |
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Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions |
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Dual-issuance of microprocessor instructions using dual dependency matrices |
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Error detection enhancement in a microprocessor through the use of a second dependency matrix |
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2009-02-03 |
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Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor |
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2008-07-15 |
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2008-04-15 |
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