Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12086600 | Branch target buffer with shared target bits | Somasundaram Arunachalam, Daren Eugene Streett | 2024-09-10 |
| 11487545 | Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methods | Daren Eugene Streett, Rami Mohammad Al Sheikh, Michael Scott McIlvaine, Robert Douglas Clancy | 2022-11-01 |
| 9715411 | Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing system | Brian R. Konigsburg, David S. Levitan, Kevin N. Magill | 2017-07-25 |
| 9395992 | Instruction swap for patching problematic instructions in a microprocessor | Ronald P. Hall, Kevin N. Magill, James O. Tingen, Todd A. Venton | 2016-07-19 |
| 8479184 | General purpose emit for use in value profiling | Venkat R. Indukuru, Alexander Erik Mericas, Mauricio J. Serrano, Zhong Liang Wang | 2013-07-02 |
| 8386712 | Structure for supporting simultaneous storage of trace and standard cache lines | Gordon Taylor Davis, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson +2 more | 2013-02-26 |
| 8131976 | Tracking effective addresses in an out-of-order processor | Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan, Balaram Sinharoy +3 more | 2012-03-06 |
| 8127115 | Group formation with multiple taken branches per group | Kevin Neal Magil, Balaram Sinharoy, Jeffrey R. Summers, James Albert Van Norstrand, Jr. | 2012-02-28 |
| 8015565 | Preventing livelocks in processor selection of load requests | John R. Patty, Steven R. Testa, Thuong Quang Truong | 2011-09-06 |
| 7996618 | Apparatus and method for using branch prediction heuristics for determination of trace formation readiness | Gordon Taylor Davis, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson +2 more | 2011-08-09 |
| 7934081 | Apparatus and method for using branch prediction heuristics for determination of trace formation readiness | Gordon Taylor Davis, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson +2 more | 2011-04-26 |
| 7836287 | Reducing the fetch time of target instructions of a predicted taken branch instruction | Brett Olsson, Kenichi Tsuchiya | 2010-11-16 |
| 7779232 | Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches | Michael O. Klett, Kevin N. Magill, Brian R. Mestan, David Mui, Balaram Sinharoy +1 more | 2010-08-17 |
| 7711930 | Apparatus and method for decreasing the latency between instruction cache and a pipeline processor | James Norris Dieffenderfer, Brian Michael Stempel, Steven R. Testa, Kenichi Tsuchiya | 2010-05-04 |
| 7707396 | Data processing system, processor and method of data processing having improved branch target address cache | Jeffrey Powers Bradford, Richard J. Eickemeyer, Wael R. El-Essawy, Douglas R. G. Logan, Balaram Sinharoy +2 more | 2010-04-27 |
| 7644233 | Apparatus and method for supporting simultaneous storage of trace and standard cache lines | Gordon Taylor Davis, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson +2 more | 2010-01-05 |
| 7610449 | Apparatus and method for saving power in a trace cache | Gordon Taylor Davis, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson +2 more | 2009-10-27 |
| 7558948 | Method for providing zero overhead looping using carry chain masking | Anthony J. Bybell, David D. Dukro | 2009-07-07 |
| 7437543 | Reducing the fetch time of target instructions of a predicted taken branch instruction | Brett Olsson, Kenichi Tsuchiya | 2008-10-14 |
| 7321954 | Method for software controllable dynamically lockable cache line replacement system | James Norris Dieffenderfer, Brian Frankel, Kenichi Tsuchiya | 2008-01-22 |
| 7305586 | Accessing and manipulating microprocessor state | Michael Stephen Floyd, Ronald Nick Kalla, John W. Ward, III | 2007-12-04 |
| 7281120 | Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor | James Norris Dieffenderfer, Brian Michael Stempel, Steven R. Testa, Kenichi Tsuchiya | 2007-10-09 |
| 6993640 | Apparatus for supporting a logically partitioned computer system | Ronald Nick Kalla, Stephen Joseph Schwinn, Edward John Silha, Kenichi Tsuchiya | 2006-01-31 |
| 6829684 | Applications of operating mode dependent error signal generation upon real address range checking prior to translation | Ronald Nick Kalla, Stephen Joseph Schwinn, Edward John Silha, Kenichi Tsuchiya | 2004-12-07 |
| 6438671 | Generating partition corresponding real address in partitioned mode supporting system | Ronald Nick Kalla, Stephen Joseph Schwinn, Edward John Silha, Kenichi Tsuchiya | 2002-08-20 |