Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8291201 | Dynamic merging of pipeline stages in an execution pipeline to reduce power consumption | Matthew R. Tubbs, Charles D. Wait | 2012-10-16 |
| 8140830 | Structural power reduction in multithreaded processor | Matthew R. Tubbs, Charles D. Wait | 2012-03-20 |
| 8082422 | Pipelined processing | — | 2011-12-20 |
| 7873816 | Pre-loading context states by inactive hardware thread in advance of context switch | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2011-01-18 |
| 7542044 | Optimized specular highlight generation | Gordon Clyde Fossum, Matthew R. Tubbs | 2009-06-02 |
| 7456837 | Optimized specular highlight generation | Gordon Clyde Fossum, Matthew R. Tubbs | 2008-11-25 |
| 7143126 | Method and apparatus for implementing power of two floating point estimation | Gordon Clyde Fossum, Matthew R. Tubbs | 2006-11-28 |
| 6993640 | Apparatus for supporting a logically partitioned computer system | Richard W. Doing, Ronald Nick Kalla, Edward John Silha, Kenichi Tsuchiya | 2006-01-31 |
| 6883116 | Method and apparatus for verifying hardware implementation of a processor architecture in a logically partitioned data processing system | Van Hoa Lee, Charles Andrew McLaughlin | 2005-04-19 |
| 6829684 | Applications of operating mode dependent error signal generation upon real address range checking prior to translation | Richard W. Doing, Ronald Nick Kalla, Edward John Silha, Kenichi Tsuchiya | 2004-12-07 |
| 6438671 | Generating partition corresponding real address in partitioned mode supporting system | Richard W. Doing, Ronald Nick Kalla, Edward John Silha, Kenichi Tsuchiya | 2002-08-20 |
| 6161166 | Instruction cache for multithreaded processor | Richard W. Doing, Ronald Nick Kalla | 2000-12-12 |