Issued Patents All Time
Showing 1–25 of 124 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10776117 | Instruction predication using unused datapath facilities | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2020-09-15 |
| 10627887 | Face detection circuit | Ryan Scott Haraden, Rob Shearer | 2020-04-21 |
| 10521234 | Concurrent multiple instruction issued of non-pipelined instructions using non-pipelined operation resources in another processing core | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2019-12-31 |
| 10310998 | Direct memory access with filtering | Ryan Scott Haraden, Robert A. Shearer, Adam J. Muff, Ashish Gupta | 2019-06-04 |
| 10261793 | Instruction predication using instruction address pattern matching | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2019-04-16 |
| 10181175 | Low power DMA snoop and skip | Ryan Scott Haraden, Adam J. Muff, Robert A. Shearer | 2019-01-15 |
| 10133300 | Control of predication across clock domains | Robert A. Shearer, Ryan Scott Haraden | 2018-11-20 |
| 10067556 | Branch prediction with power usage prediction and control | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2018-09-04 |
| 10042417 | Branch prediction with power usage prediction and control | Mark J. Hickey, Adam J. Muff, Charles D. Wait | 2018-08-07 |
| 9927862 | Variable precision in hardware pipelines for power conservation | Robert A. Shearer, Ryan Scott Haraden | 2018-03-27 |
| 9710878 | Low power DMA labeling | Ryan Scott Haraden, Adam J. Muff, Robert A. Shearer | 2017-07-18 |
| 9710274 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-07-18 |
| 9678885 | Regular expression memory region with integrated regular expression engine | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-06-13 |
| 9652239 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-05-16 |
| 9652238 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-05-16 |
| 9632786 | Instruction set architecture with extended register addressing using one or more primary opcode bits | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-04-25 |
| 9632779 | Instruction predication using instruction filtering | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-04-25 |
| 9619234 | Indirect instruction predication | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-04-11 |
| 9594562 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-03-14 |
| 9594557 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-03-14 |
| 9594556 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-03-14 |
| 9582277 | Indirect instruction predication | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-02-28 |
| 9542184 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2017-01-10 |
| 9507599 | Instruction set architecture with extensible register addressing | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2016-11-29 |
| 9501279 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Paul E. Schardt, Robert A. Shearer | 2016-11-22 |