Issued Patents All Time
Showing 25 most recent of 189 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11269690 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2022-03-08 |
| 11068318 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2021-07-20 |
| 10852810 | Adaptive power down of intra-chip interconnect | Patrick P. Lai | 2020-12-01 |
| 10831504 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Ken V. Vu +1 more | 2020-11-10 |
| 10776117 | Instruction predication using unused datapath facilities | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2020-09-15 |
| 10591978 | Cache memory with reduced power consumption mode | Patrick P. Lai | 2020-03-17 |
| 10565122 | Serial tag lookup with way-prediction | Patrick P. Lai | 2020-02-18 |
| 10545797 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2020-01-28 |
| 10534654 | Dynamic thread status retrieval using inter-thread communication | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2020-01-14 |
| 10521234 | Concurrent multiple instruction issued of non-pipelined instructions using non-pipelined operation resources in another processing core | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2019-12-31 |
| 10324850 | Serial lookup of tag ways | Patrick P. Lai | 2019-06-18 |
| 10318428 | Power aware hash function for cache memory mapping | Patrick P. Lai | 2019-06-11 |
| 10310998 | Direct memory access with filtering | Ryan Scott Haraden, Matthew R. Tubbs, Adam J. Muff, Ashish Gupta | 2019-06-04 |
| 10310548 | Expected lifetime management | Hee Jun Park, Victorya Vishnyakov | 2019-06-04 |
| 10241561 | Adaptive power down of intra-chip interconnect | Patrick P. Lai | 2019-03-26 |
| 10185378 | Prioritized sequencing of device inrush current | Jay Tsao, Jonathan Ross | 2019-01-22 |
| 10181175 | Low power DMA snoop and skip | Ryan Scott Haraden, Matthew R. Tubbs, Adam J. Muff | 2019-01-15 |
| 10133300 | Control of predication across clock domains | Matthew R. Tubbs, Ryan Scott Haraden | 2018-11-20 |
| 10114652 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Ken V. Vu +1 more | 2018-10-30 |
| 9927862 | Variable precision in hardware pipelines for power conservation | Matthew R. Tubbs, Ryan Scott Haraden | 2018-03-27 |
| 9911212 | Resetting of dynamically grown accelerated data structure | David Keith Fowler, Eric O. Mejdrich, Paul E. Schardt | 2018-03-06 |
| 9864712 | Shared receive queue allocation for network on a chip communication | Jeffrey Douglas Brown | 2018-01-09 |
| 9747225 | Interrupt controller | Tolga Ozguner, Elene Terry, Jonathan Ross | 2017-08-29 |
| 9710878 | Low power DMA labeling | Ryan Scott Haraden, Matthew R. Tubbs, Adam J. Muff | 2017-07-18 |
| 9710274 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-07-18 |