Issued Patents All Time
Showing 26–50 of 189 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9678885 | Regular expression memory region with integrated regular expression engine | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-06-13 |
| 9652239 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-05-16 |
| 9652238 | Instruction set architecture with opcode lookup using memory attribute | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-05-16 |
| 9632779 | Instruction predication using instruction filtering | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-04-25 |
| 9632786 | Instruction set architecture with extended register addressing using one or more primary opcode bits | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-04-25 |
| 9619234 | Indirect instruction predication | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-04-11 |
| 9606841 | Thread scheduling across heterogeneous processing elements with resource mapping | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2017-03-28 |
| 9600346 | Thread scheduling across heterogeneous processing elements with resource mapping | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2017-03-21 |
| 9594562 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-03-14 |
| 9594557 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-03-14 |
| 9594556 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-03-14 |
| 9582277 | Indirect instruction predication | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-02-28 |
| 9549100 | Low-latency timing control | Jonathan Ross, Elene Terry | 2017-01-17 |
| 9542184 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2017-01-10 |
| 9507599 | Instruction set architecture with extensible register addressing | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-11-29 |
| 9501279 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-11-22 |
| 9465613 | Instruction predication using unused datapath facilities | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-10-11 |
| 9405536 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-08-02 |
| 9405535 | Floating point execution unit for calculating packed sum of absolute differences | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-08-02 |
| 9378168 | Shared receive queue allocation for network on a chip communication | Jeffrey Douglas Brown | 2016-06-28 |
| 9354884 | Processor with hybrid pipeline capable of operating in out-of-order and in-order modes | Miguel Comparan, Andrew D. Hilton, Hans M. Jacobson, Brian M. Rogers, Ken V. Vu +1 more | 2016-05-31 |
| 9354887 | Instruction buffer bypass of target instruction in response to partial flush | Eric O. Mejdrich, Paul E. Schardt, Matthew R. Tubbs | 2016-05-31 |
| 9342309 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-05-17 |
| 9329870 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-05-03 |
| 9317291 | Local instruction loop buffer utilizing execution unit register file | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2016-04-19 |