Issued Patents All Time
Showing 76–100 of 189 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9092347 | Allocating cache for use as a dedicated local storage | Miguel Comparan, Russell D. Hoover, Alfred T. Watson, III | 2015-07-28 |
| 9075623 | External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit | Eric O. Mejdrich, Paul E. Schardt, Corey V. Swenson | 2015-07-07 |
| 9053037 | Allocating cache for use as a dedicated local storage | Miguel Comparan, Russell D. Hoover, Alfred T. Watson, III | 2015-06-09 |
| 9053049 | Translation management instructions for updating address translation data structures in remote processing nodes | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-06-09 |
| 9043801 | Two-tiered dynamic load balancing using sets of distributed thread pools | Mark G. Kupferschmidt, Paul E. Schardt | 2015-05-26 |
| 9041713 | Dynamic spatial index remapping for optimal aggregate performance | Jeffrey Douglas Brown, Russell D. Hoover, Eric O. Mejdrich | 2015-05-26 |
| 9032191 | Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levels | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-05-12 |
| 9021237 | Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source thread | Miguel Comparan, Russell D. Hoover, Alfred T. Watson, III | 2015-04-28 |
| 8990833 | Indirect inter-thread communication using a shared pool of inboxes | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2015-03-24 |
| 8984260 | Predecode logic autovectorizing a group of scalar instructions including result summing add instruction to a vector instruction for execution in vector unit with dot product adder | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-03-17 |
| 8954973 | Transferring architected state between cores | Miguel Comparan, Russell D. Hoover, Alfred T. Watson, III | 2015-02-10 |
| 8954755 | Memory address translation-based data encryption with integrated encryption engine | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-02-10 |
| 8949836 | Transferring architected state between cores | Miguel Comparan, Russell D. Hoover, Alfred T. Watson, III | 2015-02-03 |
| 8935694 | System and method for selectively saving and restoring state of branch prediction logic through separate hypervisor-mode and guest-mode and/or user-mode instructions | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2015-01-13 |
| 8898396 | Software pipelining on a network on chip | Eric O. Mejdrich, Paul E. Schardt | 2014-11-25 |
| 8892851 | Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2014-11-18 |
| 8856602 | Multi-core processor with internal voting-based built in self test (BIST) | Jeffrey Douglas Brown, Miguel Comparan, Alfred T. Watson, III | 2014-10-07 |
| 8843706 | Memory management among levels of cache in a memory hierarchy | Timothy H. Heil | 2014-09-23 |
| 8836709 | Vector register file caching of context data structure for maintaining state data in a multithreaded image processing pipeline | Eric O. Mejdrich, Paul E. Schardt, Matthew R. Tubbs | 2014-09-16 |
| 8773449 | Rendering of stereoscopic images with multithreaded rendering software pipeline | Russell D. Hoover, Eric O. Mejdrich, Paul E. Schardt | 2014-07-08 |
| 8776035 | Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous cores | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2014-07-08 |
| 8751830 | Memory address translation-based data encryption/compression | Adam J. Muff, Paul E. Schardt, Matthew R. Tubbs | 2014-06-10 |
| 8719455 | DMA-based acceleration of command push buffer between host and target devices | Eric O. Mejdrich, Paul E. Schardt, Matthew R. Tubbs | 2014-05-06 |
| 8719404 | Regular expression searches utilizing general purpose processors on a network interconnect | Jamie R. Kuesel, Mark G. Kupferschmidt, Paul E. Schardt | 2014-05-06 |
| 8719507 | Near neighbor data cache sharing | Miguel Comparan | 2014-05-06 |