Issued Patents All Time
Showing 25 most recent of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12048256 | Interfacing with superconducting circuitry | Miguel Comparan, Indranil S. Sen, Paul D. Berndt | 2024-07-23 |
| 11218139 | Test and characterization of ring in superconducting domain through built-in self-test | Clint Wayne Mumford, Kshitiz Saxena, Miguel Comparan, Oscar Rosell | 2022-01-04 |
| 11030369 | Superconducting circuit with virtual timing elements and related methods | Janet L. Schneider, Kenneth Reneris, Mark G. Kupferschmidt, Brian Lee Koehler, Alexander Braun +1 more | 2021-06-08 |
| 10776117 | Instruction predication using unused datapath facilities | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2020-09-15 |
| 10672368 | No miss cache structure for real-time image transformations with multiple LSR processing engines | Ryan Scott Haraden, Tolga Ozguner, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung +1 more | 2020-06-02 |
| 10521234 | Concurrent multiple instruction issued of non-pipelined instructions using non-pipelined operation resources in another processing core | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2019-12-31 |
| 10514753 | Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power | Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Gene Leung, Tolga Ozguner | 2019-12-24 |
| 10410349 | Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power | Ryan Scott Haraden, Jeffrey Powers Bradford, Miguel Comparan, Gene Leung, Tolga Ozguner | 2019-09-10 |
| 10310998 | Direct memory access with filtering | Ryan Scott Haraden, Robert A. Shearer, Matthew R. Tubbs, Ashish Gupta | 2019-06-04 |
| 10261793 | Instruction predication using instruction address pattern matching | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2019-04-16 |
| 10255891 | No miss cache structure for real-time image transformations with multiple LSR processing engines | Ryan Scott Haraden, Tolga Ozguner, Jeffrey Powers Bradford, Christopher Jon Johnson, Gene Leung +1 more | 2019-04-09 |
| 10241470 | No miss cache structure for real-time image transformations with data compression | Tolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Miguel Comparan, Ryan Scott Haraden +1 more | 2019-03-26 |
| 10242654 | No miss cache structure for real-time image transformations | Tolga Ozguner, Jeffrey Powers Bradford, Miguel Comparan, Gene Leung, Ryan Scott Haraden +1 more | 2019-03-26 |
| 10181175 | Low power DMA snoop and skip | Ryan Scott Haraden, Matthew R. Tubbs, Robert A. Shearer | 2019-01-15 |
| 10067556 | Branch prediction with power usage prediction and control | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2018-09-04 |
| 10042417 | Branch prediction with power usage prediction and control | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2018-08-07 |
| 9978118 | No miss cache structure for real-time image transformations with data compression | Tolga Ozguner, Gene Leung, Jeffrey Powers Bradford, Miguel Comparan, Ryan Scott Haraden +1 more | 2018-05-22 |
| 9971713 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +54 more | 2018-05-15 |
| 9710878 | Low power DMA labeling | Ryan Scott Haraden, Matthew R. Tubbs, Robert A. Shearer | 2017-07-18 |
| 9710274 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-07-18 |
| 9678885 | Regular expression memory region with integrated regular expression engine | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-06-13 |
| 9652239 | Instruction set architecture with opcode lookup using memory attribute | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-05-16 |
| 9652238 | Instruction set architecture with opcode lookup using memory attribute | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-05-16 |
| 9632786 | Instruction set architecture with extended register addressing using one or more primary opcode bits | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-04-25 |
| 9632779 | Instruction predication using instruction filtering | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-04-25 |