Issued Patents All Time
Showing 26–50 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9619234 | Indirect instruction predication | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-04-11 |
| 9594562 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-03-14 |
| 9594557 | Floating point execution unit for calculating packed sum of absolute differences | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-03-14 |
| 9594556 | Floating point execution unit for calculating packed sum of absolute differences | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-03-14 |
| 9582277 | Indirect instruction predication | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-02-28 |
| 9542184 | Local instruction loop buffer utilizing execution unit register file | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2017-01-10 |
| 9507599 | Instruction set architecture with extensible register addressing | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-11-29 |
| 9501279 | Local instruction loop buffer utilizing execution unit register file | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-11-22 |
| 9495724 | Single precision vector permute immediate with “word” vector write mask | Eric O. Mejdrich | 2016-11-15 |
| 9465613 | Instruction predication using unused datapath facilities | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-10-11 |
| 9424490 | System and method for classifying pixels | John Tardif, Susan Carrie, Mark J. Finocchio, Kyungsuk David Lee, Christopher Douglas Edmonds +1 more | 2016-08-23 |
| 9405536 | Floating point execution unit for calculating packed sum of absolute differences | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-08-02 |
| 9405535 | Floating point execution unit for calculating packed sum of absolute differences | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-08-02 |
| 9395804 | Branch prediction with power usage prediction and control | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2016-07-19 |
| 9342309 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-05-17 |
| 9329870 | Extensible execution unit interface architecture with multiple decode logic and multiple execution units | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-05-03 |
| 9317294 | Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing core | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-04-19 |
| 9317291 | Local instruction loop buffer utilizing execution unit register file | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-04-19 |
| 9311096 | Local instruction loop buffer utilizing execution unit register file | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-04-12 |
| 9311090 | Indirect instruction predication | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-04-12 |
| 9304771 | Indirect instruction predication | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-04-05 |
| 9292290 | Instruction set architecture with opcode lookup using memory attribute | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-03-22 |
| 9286071 | Instruction set architecture with opcode lookup using memory attribute | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-03-15 |
| 9274591 | General purpose processing unit with low power digital signal processing (DSP) mode | Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs | 2016-03-01 |
| 9262160 | Load latency speculation in an out-of-order computer processor | Timothy H. Heil, Andrew D. Hilton | 2016-02-16 |