Issued Patents All Time
Showing 76–100 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8560924 | Register file soft error recovery | Bruce M. Fleischer, Thomas W. Fox, Charles D. Wait, Alfred T. Watson, III | 2013-10-15 |
| 8549262 | Instruction operand addressing using register address sequence detection | Eric O. Mejdrich, Robert A. Shearer, Matthew R. Tubbs | 2013-10-01 |
| 8522254 | Programmable integrated processor blocks | Mark J. Hickey, Eric O. Mejdrich, Paul E. Schardt, Robert A. Shearer, Matthew R. Tubbs +1 more | 2013-08-27 |
| 8443027 | Implementing a floating point weighted average function | Matthew R. Tubbs | 2013-05-14 |
| 8412980 | Fault tolerant stability critical execution checking using redundant execution pipelines | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2013-04-02 |
| 8412760 | Dynamic range adjusting floating point execution unit | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2013-04-02 |
| 8356162 | Execution unit with data dependent conditional write instructions | Matthew R. Tubbs | 2013-01-15 |
| 8356160 | Pipelined multiple operand minimum and maximum function | Matthew R. Tubbs | 2013-01-15 |
| 8332452 | Single precision vector dot product with “word” vector write mask | Eric O. Mejdrich | 2012-12-11 |
| 8326904 | Trigonometric summation vector execution unit | Matthew R. Tubbs | 2012-12-04 |
| 8310497 | Anisotropic texture filtering with texture data prefetching | Miguel Comparan, Eric O. Mejdrich, Matthew R. Tubbs | 2012-11-13 |
| 8275821 | Area efficient transcendental estimate algorithm | Eric O. Mejdrich, Matthew R. Tubbs | 2012-09-25 |
| 8255443 | Execution unit with inline pseudorandom number generator | Matthew R. Tubbs | 2012-08-28 |
| 8255674 | Implied storage operation decode using redundant target address detection | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2012-08-28 |
| 8239439 | Method and apparatus implementing a minimal area consumption multiple addend floating point summation function in a vector microprocessor | Matthew R. Tubbs | 2012-08-07 |
| 8239438 | Method and apparatus for implementing a multiple operand vector floating point summation to scalar function | Matthew R. Tubbs | 2012-08-07 |
| 8217953 | Anisotropic texture filtering with texture data prefetching | Miguel Comparan, Eric O. Mejdrich, Matthew R. Tubbs | 2012-07-10 |
| 8169439 | Scalar precision float implementation on the “W” lane of vector unit | David Arnold Luick, Eric O. Mejdrich | 2012-05-01 |
| 8161271 | Store misaligned vector with permute | David Arnold Luick, Eric O. Mejdrich | 2012-04-17 |
| 8139061 | Floating point execution unit for calculating a one minus dot product value in a single pass | Matthew R. Tubbs | 2012-03-20 |
| 8102884 | Direct inter-thread communication buffer that supports software controlled arbitrary vector operand selection in a densely threaded network on a chip | Robert A. Shearer, Matthew R. Tubbs | 2012-01-24 |
| 8082420 | Method and apparatus for executing instructions | Miguel Comparan, Brent F. Hilgart, Brian Lee Koehler, Eric O. Mejdrich, Alfred T. Watson, III | 2011-12-20 |
| 8028153 | Data dependent instruction decode | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2011-09-27 |
| 7975172 | Redundant execution of instructions in multistage execution pipeline during unused execution cycles | Mark J. Hickey, Matthew R. Tubbs, Charles D. Wait | 2011-07-05 |
| 7945764 | Processing unit incorporating multirate execution unit | Eric O. Mejdrich, Matthew R. Tubbs | 2011-05-17 |