Issued Patents All Time
Showing 25 most recent of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182576 | Executing a composite scalar-vector VLIW instruction having a repeat field | Bruce M. Fleischer, Arpith Chacko Jacob, Hans M. Jacobson, Ravi Nair, Kevin O'Brien +1 more | 2024-12-31 |
| 11314482 | Low latency floating-point division operations | Silvia M. Mueller, Bruce M. Fleischer | 2022-04-26 |
| 10963380 | Cache miss thread balancing | Gregory W. Alexander, Brian D. Barrick, Christian Jacobi, Anthony Saporito, Somin Song +1 more | 2021-03-30 |
| 10572263 | Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution | Bruce M. Fleischer, Arpith Chacko Jacob, Hans M. Jacobson, Ravi Nair, Kevin O'Brien +1 more | 2020-02-25 |
| 10353817 | Cache miss thread balancing | Gregory W. Alexander, Brian D. Barrick, Christian Jacobi, Anthony Saporito, Somin Song +1 more | 2019-07-16 |
| 10049061 | Active memory device gather, scatter, and filter | Bruce M. Fleischer, Hans M. Jacobson, James Allan Kahle, Jaime Moreno, Ravi Nair | 2018-08-14 |
| 10007242 | Mechanism for controlling subset of devices | Hans M. Jacobson, Ravi Nair, Bryan S. Rosenburg | 2018-06-26 |
| 9971713 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +54 more | 2018-05-15 |
| 9928190 | High bandwidth low latency data exchange between processing elements | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2018-03-27 |
| 9910802 | High bandwidth low latency data exchange between processing elements | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2018-03-06 |
| 9841926 | On-chip traffic prioritization in memory | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2017-12-12 |
| 9632777 | Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry | Bruce M. Fleischer, Hans M. Jacobson, Jaime Moreno, Ravi Nair, Daniel A. Prener | 2017-04-25 |
| 9632778 | Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry | Bruce M. Fleischer, Hans M. Jacobson, Jaime Moreno, Ravi Nair, Daniel A. Prener | 2017-04-25 |
| 9594724 | Vector register file | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2017-03-14 |
| 9582466 | Vector register file | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2017-02-28 |
| 9575756 | Predication in a vector processor | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2017-02-21 |
| 9575755 | Vector processing in an active memory device | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair, Daniel A. Prener | 2017-02-21 |
| 9569211 | Predication in a vector processor | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2017-02-14 |
| 9535694 | Vector processing in an active memory device | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair, Daniel A. Prener | 2017-01-03 |
| 9405712 | On-chip traffic prioritization in memory | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2016-08-02 |
| 9405711 | On-chip traffic prioritization in memory | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2016-08-02 |
| 9400656 | Chaining between exposed vector pipelines | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2016-07-26 |
| 9389675 | Power management for in-memory computer systems | Pradip Bose, Alper Buyuktosunoglu, Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair +1 more | 2016-07-12 |
| 9390038 | Local bypass for in memory computing | Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair, Martin Ohmacht, Krishnan Sugavanam | 2016-07-12 |
| 9329664 | Power management for a computer system | Pradip Bose, Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair | 2016-05-03 |