DP

Daniel A. Prener

IBM: 28 patents #3,676 of 70,183Top 6%
Overall (All Time): #136,859 of 4,157,543Top 4%
28
Patents All Time

Issued Patents All Time

Showing 25 most recent of 28 patents

Patent #TitleCo-InventorsDate
12182576 Executing a composite scalar-vector VLIW instruction having a repeat field Bruce M. Fleischer, Thomas W. Fox, Arpith Chacko Jacob, Hans M. Jacobson, Ravi Nair +1 more 2024-12-31
11687369 Flexible optimized data handling in systems with multiple memories Tong Chen, John Kevin Patrick O'Brien, Zehra N. Sura 2023-06-27
10996989 Flexible optimized data handling in systems with multiple memories Tong Chen, John Kevin Patrick O'Brien, Zehra N. Sura 2021-05-04
10572263 Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution Bruce M. Fleischer, Thomas W. Fox, Arpith Chacko Jacob, Hans M. Jacobson, Ravi Nair +1 more 2020-02-25
9632777 Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Jaime Moreno, Ravi Nair 2017-04-25
9632778 Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Jaime Moreno, Ravi Nair 2017-04-25
9575755 Vector processing in an active memory device Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair 2017-02-21
9535694 Vector processing in an active memory device Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair 2017-01-03
9043194 Method and system for efficient emulation of multiprocessor memory consistency Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden 2015-05-26
9038040 Method for partitioning programs between a general purpose core and one or more accelerators John Kevin Patrick O'Brien, Kathryn M. O'Brien 2015-05-19
8972782 Exposed-pipeline processing element with rollback Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair 2015-03-03
8949101 Hardware execution driven application level derating calculation for soft error rate analysis Pradip Bose, Meeta S. Gupta, Prabhakar Kudva 2015-02-03
8719548 Method and system for efficient emulation of multiprocessor address translation on a multiprocessor Erik R. Altman, Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden +1 more 2014-05-06
8578351 Hybrid mechanism for more efficient emulation and method therefor Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden 2013-11-05
8375374 Partitioning programs between a general purpose core and one or more accelerators John Kevin Patrick O'Brien, Kathryn M. O'Brien 2013-02-12
8108843 Hybrid mechanism for more efficient emulation and method therefor Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden 2012-01-31
7962906 Compiler method for employing multiple autonomous synergistic processors to simultaneously operate on longer vectors of data John Kevin Patrick O'Brien, Kathryn M. O'Brien 2011-06-14
7953588 Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host Erik R. Altman, Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden +1 more 2011-05-31
7865699 Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code Erik R. Altman, Michael K. Gschwind, David Arnold Luick, Jude A. Rivers, Sumedh W. Sathaye +1 more 2011-01-04
7844446 Method and system for multiprocessor emulation on a multiprocessor host system Erik R. Altman, Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden +1 more 2010-11-30
7496494 Method and system for multiprocessor emulation on a multiprocessor host system Erik R. Altman, Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden +1 more 2009-02-24
7441110 Prefetching using future branch path information derived from branch prediction Thomas R. Puzak, Allan M. Hartstein, Mark J. Charney, Peter Howland Oden 2008-10-21
7340588 Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code Erik R. Altman, Michael K. Gschwind, David Arnold Luick, Jude A. Rivers, Sumedh W. Sathaye +1 more 2008-03-04
7146607 Method and system for transparent dynamic optimization in a multiprocessing environment Ravi Nair, John Kevin Patrick O'Brien, Kathryn M. O'Brien, Peter Howland Oden 2006-12-05
6560693 Branch history guided instruction/data prefetching Thomas R. Puzak, Allan M. Hartstein, Mark J. Charney, Peter Howland Oden, Vijayalakshmi Srinivasan 2003-05-06