Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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David Arnold Luick — 107 Patents

IBM: 107 patents #506 of 70,183Top 1%
Rochester, MN: #26 of 3,042 inventorsTop 1%
Minnesota: #174 of 52,454 inventorsTop 1%
Overall (All Time): #12,671 of 4,157,543Top 1%
107 Patents All Time
David Arnold Luick has been granted 107 US patents while listed as an inventor at IBM. The first was granted in 1981 and the most recent in August 2014. David Arnold Luick ranks #12,671 of 4,157,543 US inventors in our database (top 0.30%). Patent records list David Arnold Luick in Rochester, MN, US.

Issued Patents All Time

Showing 1–25 of 107 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8812822 Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss 2014-08-19 $3,895,000
8756404 Cascaded delayed float/vector execution pipeline 2014-06-17 $4,121,000
8429350 Cache line use history based done bit modification to D-cache replacement scheme 2013-04-23 $7,839,000
8332587 Cache line use history based done bit modification to I-cache replacement scheme 2012-12-11 $5,394,000
8301871 Predicated issue for conditional branch instructions 2012-10-30
8291169 Cache line use history based done bit modification to D-cache replacement scheme 2012-10-16 $3,795,000
8171224 D-cache line use history based done bit based on successful prefetchable counter 2012-05-01 $7,417,000
8169439 Scalar precision float implementation on the “W” lane of vector unit Eric O. Mejdrich, Adam J. Muff 2012-05-01 $7,417,000
8161271 Store misaligned vector with permute Eric O. Mejdrich, Adam J. Muff 2012-04-17 $5,847,000
8140760 I-cache line use history based done bit based on successful prefetchable counter 2012-03-20 $2,170,000
8140829 Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution Richard J. Eickemeyer 2012-03-20 $2,170,000
8135941 Vector morphing mechanism for multiple processor cores 2012-03-13 $7,610,000
8108654 System and method for a group priority issue schema for a cascaded pipeline Jeffrey Powers Bradford 2012-01-31 $4,013,000
8095779 System and method for optimization within a group priority issue schema for a cascaded pipeline 2012-01-10 $7,380,000
8019969 Self prefetching L3/L4 cache mechanism 2011-09-13 $4,804,000
8019968 3-dimensional L2/L3 cache array to hide translation (TLB) delays 2011-09-13 $4,804,000
8001361 Structure for a single shared instruction predecoder for supporting multiple processors 2011-08-16 $4,692,000
7996654 System and method for optimization within a group priority issue schema for a cascaded pipeline 2011-08-09 $2,733,000
7996655 Multiport execution target delay queue FIFO array 2011-08-09 $2,733,000
7984272 Design structure for single hot forward interconnect scheme for delayed execution pipelines 2011-07-19 $6,687,000
7984270 System and method for prioritizing arithmetic instructions 2011-07-19 $6,687,000
7945763 Single shared instruction predecoder for supporting multiple processors 2011-05-17 $5,524,000
7941654 Local and global branch prediction information storage 2011-05-10 $6,699,000
7937530 Method and apparatus for accessing a cache with an effective address 2011-05-03 $5,933,000
7882335 System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline 2011-02-01 $3,711,000