Issued Patents All Time
Showing 25 most recent of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8812822 | Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss | — | 2014-08-19 |
| 8756404 | Cascaded delayed float/vector execution pipeline | — | 2014-06-17 |
| 8429350 | Cache line use history based done bit modification to D-cache replacement scheme | — | 2013-04-23 |
| 8332587 | Cache line use history based done bit modification to I-cache replacement scheme | — | 2012-12-11 |
| 8301871 | Predicated issue for conditional branch instructions | — | 2012-10-30 |
| 8291169 | Cache line use history based done bit modification to D-cache replacement scheme | — | 2012-10-16 |
| 8171224 | D-cache line use history based done bit based on successful prefetchable counter | — | 2012-05-01 |
| 8169439 | Scalar precision float implementation on the “W” lane of vector unit | Eric O. Mejdrich, Adam J. Muff | 2012-05-01 |
| 8161271 | Store misaligned vector with permute | Eric O. Mejdrich, Adam J. Muff | 2012-04-17 |
| 8140760 | I-cache line use history based done bit based on successful prefetchable counter | — | 2012-03-20 |
| 8140829 | Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution | Richard J. Eickemeyer | 2012-03-20 |
| 8135941 | Vector morphing mechanism for multiple processor cores | — | 2012-03-13 |
| 8108654 | System and method for a group priority issue schema for a cascaded pipeline | Jeffrey Powers Bradford | 2012-01-31 |
| 8095779 | System and method for optimization within a group priority issue schema for a cascaded pipeline | — | 2012-01-10 |
| 8019969 | Self prefetching L3/L4 cache mechanism | — | 2011-09-13 |
| 8019968 | 3-dimensional L2/L3 cache array to hide translation (TLB) delays | — | 2011-09-13 |
| 8001361 | Structure for a single shared instruction predecoder for supporting multiple processors | — | 2011-08-16 |
| 7996654 | System and method for optimization within a group priority issue schema for a cascaded pipeline | — | 2011-08-09 |
| 7996655 | Multiport execution target delay queue FIFO array | — | 2011-08-09 |
| 7984272 | Design structure for single hot forward interconnect scheme for delayed execution pipelines | — | 2011-07-19 |
| 7984270 | System and method for prioritizing arithmetic instructions | — | 2011-07-19 |
| 7945763 | Single shared instruction predecoder for supporting multiple processors | — | 2011-05-17 |
| 7941654 | Local and global branch prediction information storage | — | 2011-05-10 |
| 7937530 | Method and apparatus for accessing a cache with an effective address | — | 2011-05-03 |
| 7882335 | System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline | — | 2011-02-01 |