Issued Patents All Time
Showing 26–50 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7877579 | System and method for prioritizing compare instructions | — | 2011-01-25 |
| 7870368 | System and method for prioritizing branch instructions | — | 2011-01-11 |
| 7865699 | Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, Michael K. Gschwind, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye +1 more | 2011-01-04 |
| 7865700 | System and method for prioritizing store instructions | — | 2011-01-04 |
| 7865769 | In situ register state error recovery and restart mechanism | — | 2011-01-04 |
| 7783860 | Load misaligned vector with permute and mask insert | Eric O. Mejdrich, Adam J. Muff | 2010-08-24 |
| 7769987 | Single hot forward interconnect scheme for delayed execution pipelines | — | 2010-08-03 |
| 7743237 | Register file bit and method for fast context switch | — | 2010-06-22 |
| 7730283 | Simple load and store disambiguation and scheduling at predecode | — | 2010-06-01 |
| 7730288 | Method and apparatus for multiple load instruction execution | — | 2010-06-01 |
| 7680985 | Method and apparatus for accessing a split cache directory | — | 2010-03-16 |
| 7676656 | Minimizing unscheduled D-cache miss pipeline stalls in a cascaded delayed execution pipeline | — | 2010-03-09 |
| 7594078 | D-cache miss prediction and scheduling | — | 2009-09-22 |
| 7487340 | Local and global branch prediction information storage | — | 2009-02-03 |
| 7487330 | Method and apparatus for transferring control in a computer system with dynamic compilation capability | Erik R. Altman, Kemal Ebcioglu, Michael K. Gschwind | 2009-02-03 |
| 7461238 | Simple load and store disambiguation and scheduling at predecode | — | 2008-12-02 |
| 7454654 | Multiple parallel pipeline processor having self-repairing capability | — | 2008-11-18 |
| 7447879 | Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss | — | 2008-11-04 |
| 7343480 | Single cycle context switching by swapping a primary latch value and a selected secondary latch value in a register file | — | 2008-03-11 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, Michael K. Gschwind, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye +1 more | 2008-03-04 |
| 7302524 | Adaptive thread ID cache mechanism for autonomic performance tuning | — | 2007-11-27 |
| 7278011 | Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table | Susan E. Eisen, Hung Q. Le, Dung Q. Nguyen | 2007-10-02 |
| 7272751 | Error detection during processor idle cycles | Thomas J. Beacom | 2007-09-18 |
| 7266721 | Runtime repairable processor | — | 2007-09-04 |
| 7237094 | Instruction group formation and mechanism for SMT dispatch | Brian W. Curran, Brian R. Konigsburg, Hung Q. Le, Dung Q. Nguyen | 2007-06-26 |