Issued Patents All Time
Showing 76–100 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6922714 | Floating point unit power reduction scheme | — | 2005-07-26 |
| 6922767 | System for allowing only a partial value prediction field/cache size | Richard J. Eickemeyer | 2005-07-26 |
| 6912649 | Scheme to encode predicted values into an instruction stream/cache without additional bits/area | — | 2005-06-28 |
| 6910104 | Icache-based value prediction mechanism | — | 2005-06-21 |
| 6901504 | Result forwarding of either input operand to same operand input to reduce forwarding path | — | 2005-05-31 |
| 6877069 | History-based carry predictor for data cache address generation | — | 2005-04-05 |
| 6868489 | Carry generation in address calculation | — | 2005-03-15 |
| 6868033 | Dual array read port functionality from a one port SRAM | Anthony Gus Aipperspach | 2005-03-15 |
| 6823430 | Directoryless L0 cache for stall reduction | — | 2004-11-23 |
| 6804759 | Method and apparatus for detecting pipeline address conflict using compare of byte addresses | — | 2004-10-12 |
| 6775735 | Instruction pair detection and pseudo ports for cache array | — | 2004-08-10 |
| 6763421 | Instruction pair detection and pseudo ports for cache array | — | 2004-07-13 |
| 6728842 | Cache updating in multiprocessor systems | Jeffrey Douglas Brown, Steven R. Kunkel | 2004-04-27 |
| 6473835 | Partition of on-chip memory buffer for cache | — | 2002-10-29 |
| 6349362 | Scheme to partition a large lookaside buffer into an L2 cache array | — | 2002-02-19 |
| 6314493 | Branch history cache | — | 2001-11-06 |
| 6230260 | Circuit arrangement and method of speculative instruction execution utilizing instruction history caching | — | 2001-05-08 |
| 6223208 | Moving data in and out of processor units using idle register/storage functional units | Kenneth J. Kiefer, John C. Willis | 2001-04-24 |
| 6112299 | Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching | Kemal Ebcioglu, Kenneth J. Kiefer, Gabriel M. Silberman, Philip Braun Winterfield | 2000-08-29 |
| 6088769 | Multiprocessor cache coherence directed by combined local and global tables | John C. Willis, Philip Braun Winterfield | 2000-07-11 |
| 6065107 | System for restoring register data in a pipelined data processing system using latch feedback assemblies | — | 2000-05-16 |
| 5924117 | Multi-ported and interleaved cache memory supporting multiple simultaneous accesses thereto | — | 1999-07-13 |
| 5890009 | VLIW architecture and method for expanding a parcel | Philip Braun Winterfield | 1999-03-30 |
| 5875346 | System for restoring register data in a pipelined data processing system using latch feedback assemblies | — | 1999-02-23 |
| 5872990 | Reordering of memory reference operations and conflict resolution via rollback in a multiprocessing environment | John C. Willis, Philip Braun Winterfield | 1999-02-16 |