Issued Patents All Time
Showing 25 most recent of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10216557 | Method and apparatus for monitoring and enhancing on-chip microprocessor reliability | Pradip Bose, Jayanth Srinivasan | 2019-02-26 |
| 9740496 | Processor with memory-embedded pipeline for table-driven computation | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Vijayalakshmi Srinivasan | 2017-08-22 |
| 9740497 | Processor with memory-embedded pipeline for table-driven computation | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Vijayalakshmi Srinivasan | 2017-08-22 |
| 9431084 | Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Vijayalakshmi Srinivasan | 2016-08-30 |
| 9418721 | Determining and storing bit error rate relationships in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Vijayalakshmi Srinivasan | 2016-08-16 |
| 9406368 | Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Vijayalakshmi Srinivasan | 2016-08-02 |
| 9390989 | Enhanced modularity in heterogeneous 3D stacks | Philip G. Emma, Eren Kursun | 2016-07-12 |
| 9373557 | Enhanced modularity in heterogeneous 3D stacks | Philip G. Emma, Eren Kursun | 2016-06-21 |
| 9351899 | Dynamic temperature adjustments in spin transfer torque magnetoresistive random-access memory (STT-MRAM) | Pradip Bose, Alper Buyuktosunoglu, Xiaochen Guo, Hillery C. Hunter, Vijayalakshmi Srinivasan | 2016-05-31 |
| 9122513 | Method and apparatus for efficient execution of concurrent processes on a multithreaded message passing system | Arpith Chacko Jacob | 2015-09-01 |
| 9116738 | Method and apparatus for efficient execution of concurrent processes on a multithreaded message passing system | Arpith Chacko Jacob | 2015-08-25 |
| 8796047 | Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip | Pradip Bose, Eren Kursun, Victor Zyuban | 2014-08-05 |
| 8679861 | Semiconductor chip repair by stacking of a base semiconductor chip and a repair semiconductor chip | Pradip Bose, Eren Kursun, Victor Zyuban | 2014-03-25 |
| 8677613 | Enhanced modularity in heterogeneous 3D stacks | Eren Kursun, Philip G. Emma | 2014-03-25 |
| 8595731 | Low overhead dynamic thermal management in many-core cluster architecture | Pradip Bose, Philip G. Emma, Eren Kursun | 2013-11-26 |
| 8589762 | Adaptive multi-bit error correction in endurance limited memories | Vijayalakshmi Srinivasan | 2013-11-19 |
| 8589662 | Accepting or rolling back execution of instructions based on comparing predicted and actual dependency control signals | Erik R. Altman, Michael K. Gschwind, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2013-11-19 |
| 8151092 | Control signal memoization in a multiple instruction issue microprocessor | Erik R. Altman, Michael K. Gschwind, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2012-04-03 |
| 8141020 | Temperature-controlled 3-dimensional bus placement | Philip G. Emma, Eren Kursun | 2012-03-20 |
| 8108714 | Method and system for soft error recovery during processor execution | Pradip Bose, Victor Zyuban | 2012-01-31 |
| 8091050 | Modeling system-level effects of soft errors | Pradip Bose, Prabhakar Kudva, Pia Naoko Sanda, John-David Wellman | 2012-01-03 |
| 7958334 | Method and apparatus for an efficient multi-path trace cache design | Galen Arthur Rasche, Vijayalakshmi Srinivasan | 2011-06-07 |
| 7930525 | Method and apparatus for an efficient multi-path trace cache design | Galen Arthur Rasche, Vijayalakshmi Srinivasan | 2011-04-19 |
| 7921331 | Write filter cache method and apparatus for protecting the microprocessor core from soft errors | Pradip Bose, Zhigang Hu, Xiaodong Li | 2011-04-05 |
| 7865699 | Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, Michael K. Gschwind, David Arnold Luick, Daniel A. Prener, Sumedh W. Sathaye +1 more | 2011-01-04 |