Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7774654 | Method and apparatus for preventing soft error accumulation in register arrays | Pradip Bose, Balaram Sinharoy, Victor Zyuban | 2010-08-10 |
| 7552277 | Distributed buffer integrated cache memory organization and method for reducing energy consumption thereof | — | 2009-06-23 |
| 7506216 | System and method of workload-dependent reliability projection and monitoring for microprocessor chips and systems | Pradip Bose, Jayanth Srinivasan | 2009-03-17 |
| 7496733 | System and method of execution of register pointer instructions ahead of instruction issues | Erik R. Altman, Michael K. Gschwind, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2009-02-24 |
| 7493523 | Method and apparatus for preventing soft error accumulation in register arrays | Pradip Bose, Balaram Sinharoy, Victor Zyuban | 2009-02-17 |
| 7472038 | Method of predicting microprocessor lifetime reliability using architecture-level structure-aware techniques | Pradip Bose, Zhigang Hu, Jeonghee Shin, Victor Zyuban | 2008-12-30 |
| 7461209 | Transient cache storage with discard function for disposable data | Erik R. Altman, Michael K. Gschwind, Robert K. Montoye, Sumedh W. Sathaye, John-David Wellman +1 more | 2008-12-02 |
| 7454316 | Method and apparatus for monitoring and enhancing on-chip microprocessor reliability | Pradip Bose, Jayanth Srinivasan | 2008-11-18 |
| 7454573 | Cost-conscious pre-emptive cache line displacement and relocation mechanisms | Alper Buyuktosunoglu, Zhigang Hu, John T. Robinson, Xiaowei Shen, Vijayalakshmi Srinivasan | 2008-11-18 |
| 7444544 | Write filter cache method and apparatus for protecting the microprocessor core from soft errors | Pradip Bose, Zhigang Hu, Xiaodong Li | 2008-10-28 |
| 7366875 | Method and apparatus for an efficient multi-path trace cache design | Galen Arthur Rasche, Vijayalakshmi Srinivasan | 2008-04-29 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code | Erik R. Altman, Michael K. Gschwind, David Arnold Luick, Daniel A. Prener, Sumedh W. Sathaye +1 more | 2008-03-04 |
| 7325124 | System and method of execution of register pointer instructions ahead of instruction issue | Erik R. Altman, Michael K. Gschwind, Sumedh W. Sathaye, John-David Wellman, Victor Zyuban | 2008-01-29 |
| 7130963 | System and method for instruction memory storage and processing based on backwards branch control information | Sameh W. Asaad, Jaime Moreno, John-David Wellman | 2006-10-31 |
| 7076681 | Processor with demand-driven clock throttling power reduction | Pradip Bose, Daniel Citron, Peter W. Cook, Philip G. Emma, Hans M. Jacobson +3 more | 2006-07-11 |
| 6948051 | Method and apparatus for reducing logic activity in a microprocessor using reduced bit width slices that are enabled or disabled depending on operation width | Jaime Moreno, Vinodh R. Cuppu | 2005-09-20 |
| 6711651 | Method and apparatus for history-based movement of shared-data in coherent cache memories of a multiprocessor system using push prefetching | Jaime Moreno, John-David Wellman | 2004-03-23 |
| 6678795 | Method and apparatus for memory prefetching based on intra-page usage history | Jaime Moreno, John-David Wellman | 2004-01-13 |