Issued Patents All Time
Showing 25 most recent of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12072842 | Software-based log management | Wencheng Lu, Xiaoxuan Dong, Joseph Shi, Celine Ling Xu | 2024-08-27 |
| 12045159 | Automation test accelerator | Celine Ling Xu, Jinghui Zhang, Xiaoxuan Dong, Wencheng Lu | 2024-07-23 |
| 10623822 | Virtual cable modem termination system redundancy | Yuliang Chen, Jian-Hung Chen, Yu-Chan Lo | 2020-04-14 |
| 10098236 | Use of combined masking techniques and/or combined material removal techniques to protectively coat electronic devices | Vimal Kumar Kasagani, Colin LaMar Loose, Tyler Christensen Child, Caleb Edward Kanavel, Heidi L. Popeck +2 more | 2018-10-09 |
| 9141547 | Architecture support of best-effort atomic transactions for multiprocessor systems | — | 2015-09-22 |
| 9021482 | Reordering data responses using ordered indicia in a linked list | Brinda Ganesh, Jessica Hui-Chun Tseng | 2015-04-28 |
| 9003169 | Systems and methods for indirect register access using status-checking and status-setting instructions | David F. Bacon | 2015-04-07 |
| 8799581 | Cache coherence monitoring and feedback | David F. Bacon, Robert W. Wisniewski, Orran Krieger | 2014-08-05 |
| 8789028 | Memory access monitoring | Peter F. Sweeney | 2014-07-22 |
| 8671248 | Architecture support of memory access coloring | Robert W. Wisniewski, Orran Krieger | 2014-03-11 |
| 8190824 | Cache line replacement monitoring and profiling | Yefim Shuf, Peter F. Sweeney | 2012-05-29 |
| 8166255 | Reservation required transactions | Karin Strauss | 2012-04-24 |
| 8140764 | System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory | Balaram Sinharoy, Robert B. Tremaine, Robert W. Wisniewski | 2012-03-20 |
| 8140828 | Handling transaction buffer overflow in multiprocessor by re-executing after waiting for peer processors to complete pending transactions and bypassing the buffer | Hua Wang, Kun Wang | 2012-03-20 |
| 8131938 | Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systems | Man Cheuk Ng, Aaron C. Sawdey | 2012-03-06 |
| 8131894 | Method and system for a sharing buffer | Harold W. Cain, III, Rui Hou, Huayong Wang | 2012-03-06 |
| 7945741 | Reservation required transactions | Karin Strauss | 2011-05-17 |
| 7934061 | Methods and arrangements to manage on-chip memory to reduce memory latency | Dilma M. Da Silva, Elmootazbellah Nabil Elnozahy, Orran Krieger, Hazim Shafi, Balaram Sinharoy +1 more | 2011-04-26 |
| 7913048 | Data subscribe-and-publish mechanisms and methods for producer-consumer pre-fetch communications | — | 2011-03-22 |
| 7913041 | Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint | Balaram Sinharoy, Robert B. Tremaine, Robert W. Wisniewski | 2011-03-22 |
| 7904657 | Cache residence prediction | Jaehyuk Huh, Balaram Sinharoy | 2011-03-08 |
| 7895392 | Color-based cache monitoring | David F. Bacon, Robert W. Wisniewski, Orran Krieger | 2011-02-22 |
| 7856535 | Adaptive snoop-and-forward mechanisms for multiprocessor systems | Karin Strauss | 2010-12-21 |
| 7844778 | Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements | Balaram Sinharoy, Robert W. Wisniewski | 2010-11-30 |
| 7676637 | Location-aware cache-to-cache transfers | Jaehyuk Huh, Balaram Sinharoy | 2010-03-09 |