Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7634642 | Mechanism to save and restore cache and translation trace for fast context switch | Peter Hochschild, Balaram Sinharoy, Robert W. Wisniewski | 2009-12-15 |
| 7574562 | Latency-aware thread scheduling in non-uniform cache architecture systems | Balaram Sinharoy, Robert W. Wisniewski | 2009-08-11 |
| 7568073 | Mechanisms and methods of cache coherence in network-based multiprocessor systems with ring-based snoop response collection | Karin Strauss | 2009-07-28 |
| 7516306 | Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies | David F. Bacon | 2009-04-07 |
| 7478197 | Adaptive mechanisms for supplying volatile data copies in multiprocessor systems | Man Cheuk Ng, Aaron C. Sawdey | 2009-01-13 |
| 7467280 | Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache | Balaram Sinharoy, Robert B. Tremaine, Robert W. Wisniewski | 2008-12-16 |
| 7457926 | Cache line replacement monitoring and profiling | Yefim Shuf, Peter F. Sweeney | 2008-11-25 |
| 7457922 | Cache line placement prediction for multiprocessor non-uniform cache architecture systems | — | 2008-11-25 |
| 7454573 | Cost-conscious pre-emptive cache line displacement and relocation mechanisms | Alper Buyuktosunoglu, Zhigang Hu, Jude A. Rivers, John T. Robinson, Vijayalakshmi Srinivasan | 2008-11-18 |
| 7437520 | Adaptive snoop-and-forward mechanisms for multiprocessor systems | Karin Strauss | 2008-10-14 |
| 7437517 | Methods and arrangements to manage on-chip memory to reduce memory latency | Dilma M. Da Silva, Elmootazbellah Nabil Elnozahy, Orran Krieger, Hazim Shafi, Balaram Sinharoy +1 more | 2008-10-14 |
| 7395407 | Mechanisms and methods for using data access patterns | Hazim Shafi | 2008-07-01 |
| 7392352 | Computer architecture for shared memory access | Arvind Mithal, Lawrence S. Rogel | 2008-06-24 |
| 7350034 | Architecture support of best-effort atomic transactions for multiprocessor systems | — | 2008-03-25 |
| 7343454 | Methods to maintain triangle ordering of coherence messages | — | 2008-03-11 |
| 7308538 | Scope-based cache coherence | — | 2007-12-11 |
| 7287122 | Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing | Ramakrishnan Rajamony, Balaram Sinharoy | 2007-10-23 |
| 7266642 | Cache residence prediction | Jaehyuk Huh, Balaram Sinharoy | 2007-09-04 |
| 7228388 | Enabling and disabling cache bypass using predicted cache line usage | Zhigang Hu, John T. Robinson, Balaram Sinharoy | 2007-06-05 |
| 6757787 | Adaptive cache coherence protocols | Arvind Mithal, Lawrence S. Rogel | 2004-06-29 |
| 6636950 | Computer architecture for shared memory access | Arvind Mithal, Lawrence S. Rogel | 2003-10-21 |
| 6526481 | Adaptive cache coherence protocols | Arvind Mithal, Lawrence S. Rogel | 2003-02-25 |