Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12248808 | Methods and apparatus for task relocation based on memory access patterns | Rolf Riesen, Rajesh Poornachandran | 2025-03-11 |
| 9733995 | Scalable synchronization mechanism for distributed memory | Clement T. Cole, James Dinan, Gabriele Jost, Stanley C. Smith, Jr., Keith D. Underwood | 2017-08-15 |
| 8869153 | Quality of service scheduling for simultaneous multi-threaded processors | Orran Krieger, Bryan S. Rosenburg, Robert B. Tremaine | 2014-10-21 |
| 8838944 | Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded, fetch-and-decrement-bounded and store-on-twin synchronization primitives | Dong Chen, Alana Gara, Philip Heidelberger, Sameer Kumar, Martin Ohmacht +1 more | 2014-09-16 |
| 8806177 | Prefetch engine based translation prefetching | Orran Krieger, Balaram Sinharoy, Robert B. Tremaine | 2014-08-12 |
| 8799581 | Cache coherence monitoring and feedback | Xiaowei Shen, David F. Bacon, Orran Krieger | 2014-08-05 |
| 8671248 | Architecture support of memory access coloring | Xiaowei Shen, Orran Krieger | 2014-03-11 |
| 8595463 | Memory architecture with policy based data storage | Robert B. Tremaine | 2013-11-26 |
| 8543722 | Message passing with queues and channels | Gabor J. Dozsa, Philip Heidelberger, Sameer Kumar, Joseph D. Ratterman, Burkhard Steinmacher-Burow | 2013-09-24 |
| 8495649 | Scheduling threads having complementary functional unit usage on SMT processors | Orran Krieger, Bryan S. Rosenburg, Balaram Sinharoy, Robert B. Tremaine | 2013-07-23 |
| 8495318 | Memory page management in a tiered memory system | Robert B. Tremaine | 2013-07-23 |
| 8140764 | System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory | Xiaowei Shen, Balaram Sinharoy, Robert B. Tremaine | 2012-03-20 |
| 8051276 | Operating system thread scheduling for optimal heat dissipation | Orran Krieger, Bryan S. Rosenburg, Robert B. Tremaine | 2011-11-01 |
| 7913041 | Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint | Xiaowei Shen, Balaram Sinharoy, Robert B. Tremaine | 2011-03-22 |
| 7895392 | Color-based cache monitoring | Xiaowei Shen, David F. Bacon, Orran Krieger | 2011-02-22 |
| 7844778 | Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements | Xiaowei Shen, Balaram Sinharoy | 2010-11-30 |
| 7634642 | Mechanism to save and restore cache and translation trace for fast context switch | Peter Hochschild, Xiaowei Shen, Balaram Sinharoy | 2009-12-15 |
| 7574562 | Latency-aware thread scheduling in non-uniform cache architecture systems | Xiaowei Shen, Balaram Sinharoy | 2009-08-11 |
| 7467280 | Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache | Xiaowei Shen, Balaram Sinharoy, Robert B. Tremaine | 2008-12-16 |