Issued Patents All Time
Showing 1–25 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11886345 | Server recovery from a change in storage control chip | — | 2024-01-30 |
| 11449424 | Server recovery from a change in storage control chip | — | 2022-09-20 |
| 11316713 | Virtual drawers in a server | Harald Huels | 2022-04-26 |
| 11281474 | Partial computer processor core shutoff | Thilo Maurer, Markus Buehler, Arni Ingimundarson | 2022-03-22 |
| 11119927 | Coordination of cache memory operations | — | 2021-09-14 |
| 10891228 | Cache line states identifying memory cache | — | 2021-01-12 |
| 10885115 | Accessing an N-way linked list | — | 2021-01-05 |
| 10834672 | Power management of network links | Dong Chen, Paul W. Coteus, Noel A. Eisley, Philip Heidelberger, Robert M. Senger +1 more | 2020-11-10 |
| 10831493 | Hardware apparatus to measure memory locality | Markus Buehler, Arni Ingimundarson, Thilo Maurer, Benedikt Rombach | 2020-11-10 |
| 10812416 | Reduced number of counters for reliable messaging | Sameer Kumar, Philip Heidelberger, Dong Chen, Yutaka Sugawara, Robert M. Senger | 2020-10-20 |
| 10740097 | Embedding global barrier and collective in a torus network | Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Philip Heidelberger +4 more | 2020-08-11 |
| 10733103 | Non-blocking directory-based cache coherence | — | 2020-08-04 |
| 10599590 | Uniform memory access architecture | — | 2020-03-24 |
| 10601735 | Coalescing messages using a network interface controller | — | 2020-03-24 |
| 10255184 | Memory access architecture with coherence | — | 2019-04-09 |
| 10198373 | Uniform memory access architecture | — | 2019-02-05 |
| 10169261 | Address layout over physical memory | — | 2019-01-01 |
| 10152450 | Remote processing and memory utilization | Dong Chen, Noel A. Eisley, Philip Heidelberger, James Allan Kahle, Fabrizio Petrini +2 more | 2018-12-11 |
| 10114772 | Address layout over physical memory | — | 2018-10-30 |
| 10069599 | Collective network for computer structures | Matthias A. Blumrich, Paul W. Coteus, Dong Chen, Alan Gara, Mark E. Giampapa +4 more | 2018-09-04 |
| 10009296 | Coalescing messages using a network interface controller | — | 2018-06-26 |
| 9971713 | Multi-petascale highly efficient parallel supercomputer | Sameh W. Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle +54 more | 2018-05-15 |
| 9953004 | Data processing system with main and balcony boards | — | 2018-04-24 |
| 9940128 | Conditional access with timeout | — | 2018-04-10 |
| 9934077 | Reader-writer lock | — | 2018-04-03 |