Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11281474 | Partial computer processor core shutoff | Thilo Maurer, Arni Ingimundarson, Burkhard Steinmacher-Burow | 2022-03-22 |
| 10831493 | Hardware apparatus to measure memory locality | Burkhard Steinmacher-Burow, Arni Ingimundarson, Thilo Maurer, Benedikt Rombach | 2020-11-10 |
| 9760669 | Congestion mitigation by wire ordering | Diwesh Pandey, Sven Peyer | 2017-09-12 |
| 8756538 | Parsing data representative of a hardware design into commands of a hardware design environment | Hans-Werner Anderson, Uwe Brandt, Katherine Eve, Thomas Kalla, Jens Noack +1 more | 2014-06-17 |
| 8731858 | Method and system for calculating timing delay in a repeater network in an electronic circuit | Juergen Kuehl, Markus Olbrich, Philipp Panitz | 2014-05-20 |
| 8627263 | Gate configuration determination and selection from standard cell library | Thomas Buechner, Markus Olbrich, Philipp Panitz, Lei Wang | 2014-01-07 |
| 8612911 | Estimating power consumption of an electronic circuit | Thomas Buechner, Philipp Panitz, Lei Wang, Markus Olbrich | 2013-12-17 |
| 8513663 | Signal repowering chip for 3-dimensional integrated circuit | Sebastian Ehrenreich, Juergen Koehl | 2013-08-20 |
| 8495286 | Write buffer for improved DRAM write access patterns | Cagri Balkesen, Rainer Dorsch, Guenther Hutzl, Michael Kaufmann, Daniel Pfefferkorn +3 more | 2013-07-23 |
| 8407654 | Glitch power reduction | Thomas Buechner, Markus Olbrich, Philipp Panitz, Lei Wang | 2013-03-26 |
| 8380737 | Computing intersection of sets of numbers | Cagri Balkesen, Rainer Dorsch, Guenther Hutzl, Michael Kaufmann, Daniel Pfefferkorn +3 more | 2013-02-19 |
| 8234594 | Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Jason D. Hibbeler, Juergen Koehl, Edward J. Nowak | 2012-07-31 |
| 8032851 | Structure for an integrated circuit design for reducing coupling between wires of an electronic circuit | Moussadek Belaidi, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search +2 more | 2011-10-04 |
| 8015527 | Routing of wires of an electronic circuit | Juergen Koehl, Markus Olbrich, Philipp Panitz | 2011-09-06 |
| 8010916 | Test yield estimate for semiconductor products created from a library | Jeanne P. Bickford, Jason D. Hibbeler, Juergen Koehl | 2011-08-30 |
| 8010925 | Method and system for placement of electric circuit components in integrated circuit design | Juergen Koehl | 2011-08-30 |
| 8006208 | Reducing coupling between wires of an electronic circuit | Moussadek Belaidi, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search +2 more | 2011-08-23 |
| 7996808 | Computer readable medium, system and associated method for designing integrated circuits with loop insertions | Andreas H. A. Arp, Jeanne P. Bickford, Juergen Koehl, Philipp Salz | 2011-08-09 |
| 7984394 | Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Jason D. Hibbeler, Juergen Koehl, Edward J. Nowak | 2011-07-19 |
| 7960836 | Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same | Brent A. Anderson, Jeanne P. Bickford, Jason D. Hibbeler, Juergen Koehl, Edward J. Nowak | 2011-06-14 |
| 7962881 | Via structure to improve routing of wires within an integrated circuit | Ankit Gangwar, Juergen Koehl, Arun Kumar Mishra | 2011-06-14 |
| 7904861 | Method, system, and computer program product for coupled noise timing violation avoidance in detailed routing | Moussadek Belaidi, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search +2 more | 2011-03-08 |
| 7398485 | Yield optimization in router for systematic defects | Jeanne P. Bickford, Jason D. Hibbeler, Juergen Koehl, Daniel N. Maynard | 2008-07-08 |
| 7386815 | Test yield estimate for semiconductor products created from a library | Jeanne P. Bickford, Jason D. Hibbeler, Juergen Koehl | 2008-06-10 |
| 7308669 | Use of redundant routes to increase the yield and reliability of a VLSI layout | John M. Cohn, David J. Hathaway, Jason D. Hibbeler, Juergen Koehl | 2007-12-11 |