Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10175297 | Measuring a slew rate on-chip | Fatih Cilek, Michael V. Koch, Christian I. Menolfi, Dieter Nissler, Matthias Ringe | 2019-01-08 |
| 9754063 | Reducing dynamic clock skew and/or slew in an electronic circuit | Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Matthias Ringe | 2017-09-05 |
| 9319030 | Integrated circuit failure prediction using clock duty cycle recording and analysis | Thomas Gentner, Klaus P. Gungl | 2016-04-19 |
| 9306547 | Duty cycle adjustment with error resiliency | Andreas H. A. Arp, Fatih Cilek, Michael V. Koch, Christian I. Menolfi, Dieter Nissler +1 more | 2016-04-05 |
| 8937494 | Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit | Andreas H. A. Arp, Michael V. Koch, Matthias Ringe | 2015-01-20 |
| 8912824 | Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit | Andreas H. A. Arp, Michael V. Koch, Matthias Ringe | 2014-12-16 |
| 8566771 | Automation of interconnect and routing customization | Andreas H. A. Arp, Florian Braun, Michael V. Koch, Matthias Ringe | 2013-10-22 |
| 8495286 | Write buffer for improved DRAM write access patterns | Cagri Balkesen, Markus Buehler, Rainer Dorsch, Michael Kaufmann, Daniel Pfefferkorn +3 more | 2013-07-23 |
| 8380737 | Computing intersection of sets of numbers | Cagri Balkesen, Markus Buehler, Rainer Dorsch, Michael Kaufmann, Daniel Pfefferkorn +3 more | 2013-02-19 |
| 7886245 | Structure for optimizing the signal time behavior of an electronic circuit design | Stephan Held, Juergen Koehl, Bernhard Korte, Jens Massberg, Matthias Ringe +1 more | 2011-02-08 |
| 7844931 | Method and computer system for optimizing the signal time behavior of an electronic circuit design | Stephan Held, Juergen Koehl, Bernhard Korte, Jens Massberg, Matthias Ringe +1 more | 2010-11-30 |