Issued Patents All Time
Showing 25 most recent of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9798528 | Software solution for cooperative memory-side and processor-side data prefetching | Yaoqing Gao, Gheorghe C. Cascaval, Allan H. Kielstra, Michael Wazlowski, Lixin Zhang | 2017-10-24 |
| 9384108 | Functional built-in self test for a chip | Kevin M. Mcilvain, Gary A. Van Huben | 2016-07-05 |
| 9325534 | Configurable differential to single ended IO | Frank D. Ferraiolo, Kevin C. Gower, Kenneth L. Wright | 2016-04-26 |
| 9300298 | Programmable logic circuit using three-dimensional stacking techniques | Edgar R. Cordero | 2016-03-29 |
| 9166587 | Soft error resilient FPGA | Luiz C. Alves, William J. Clarke, K. Paul Muller | 2015-10-20 |
| 9106252 | Selective recompression of a string compressed by a plurality of diverse lossless compression techniques | Kanak B. Agarwal, Damir A. Jamsek, Michael A. Paolini | 2015-08-11 |
| 9106251 | Data compression utilizing longest common subsequence template | Kanak B. Agarwal, Damir A. Jamsek, Michael A. Paolini | 2015-08-11 |
| 9086957 | Requesting a memory space by a memory controller | Edgar R. Cordero, Varkey K. Varghese, Diyanesh Babu C. Vidyapoornachary | 2015-07-21 |
| 9052840 | Accessing additional memory space with multiple processors | Edgar R. Cordero, Anand Haridass, Diyanesh Babu C. Vidyapoornachary | 2015-06-09 |
| 9047057 | Accessing additional memory space with multiple processors | Edgar R. Cordero, Anand Haridass, Diyanesh Babu C. Vidyapoornachary | 2015-06-02 |
| 8949837 | Assist thread for injecting cache memory in a microprocessor | Patrick J. Bohrer, Orran Krieger, Ramakrishnan Rajamony, Michael Rosenfield, Hazim Shafi +1 more | 2015-02-03 |
| 8869153 | Quality of service scheduling for simultaneous multi-threaded processors | Orran Krieger, Bryan S. Rosenburg, Robert W. Wisniewski | 2014-10-21 |
| 8850115 | Memory package utilizing at least two types of memories | — | 2014-09-30 |
| 8806177 | Prefetch engine based translation prefetching | Orran Krieger, Balaram Sinharoy, Robert W. Wisniewski | 2014-08-12 |
| 8692561 | Implementing chip to chip calibration within a TSV stack | Edgar R. Cordero, Divya Kumar, Anuwat Saetow | 2014-04-08 |
| 8674856 | Data compression utilizing longest common subsequence template | Kanak B. Agarwal, Damir A. Jamsek, Michael A. Paolini | 2014-03-18 |
| 8618960 | Selective recompression of a string compressed by a plurality of diverse lossless compression techniques | Kanak B. Agarwal, Damir A. Jamsek, Michael A. Paolini | 2013-12-31 |
| 8595463 | Memory architecture with policy based data storage | Robert W. Wisniewski | 2013-11-26 |
| 8555234 | Verification of soft error resilience | Mark A. Check, Pia Naoko Sanda, Prabhakar Kudva | 2013-10-08 |
| 8516409 | Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device | Paul W. Coteus, Kyu-hyoun Kim | 2013-08-20 |
| 8513972 | Soft error resilient FPGA | Luiz C. Alves, William J. Clarke, K. Paul Muller | 2013-08-20 |
| 8495649 | Scheduling threads having complementary functional unit usage on SMT processors | Orran Krieger, Bryan S. Rosenburg, Balaram Sinharoy, Robert W. Wisniewski | 2013-07-23 |
| 8495328 | Providing frame start indication in a memory system having indeterminate read data latency | Paul W. Coteus, Kevin C. Gower, Warren E. Maule | 2013-07-23 |
| 8495318 | Memory page management in a tiered memory system | Robert W. Wisniewski | 2013-07-23 |
| 8493801 | Strobe offset in bidirectional memory strobe configurations | Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann +3 more | 2013-07-23 |