Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
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Robert B. Tremaine — 73 Patents

IBM: 73 patents #977 of 70,183Top 2%
Stormville, NY: #5 of 88 inventorsTop 6%
New York: #1,004 of 115,490 inventorsTop 1%
Overall (All Time): #27,289 of 4,157,543Top 1%
73 Patents All Time

Issued Patents All Time

Showing 26–50 of 73 patents

Patent #TitleCo-InventorsDate
8493089 Programmable logic circuit using three-dimensional stacking techniques Edgar R. Cordero 2013-07-23
8490065 Method and apparatus for software-assisted data cache and prefetch control Roch G. Archambault, Yaoqing Gao, Francis Patrick O'Connell, Michael Wazlowski, Steven Wayne White +1 more 2013-07-16
8433950 System to determine fault tolerance in an integrated circuit and associated methods Mark A. Check, Andrew R. Ranck 2013-04-30
8327105 Providing frame start indication in a memory system having indeterminate read data latency Paul W. Coteus, Kevin C. Gower, Warren E. Maule 2012-12-04
8284621 Strobe offset in bidirectional memory strobe configurations Daniel M. Dreps, Kevin C. Gower, Michael K. Kerr, Kyu-hyoun Kim, David W. Mann +3 more 2012-10-09
8230422 Assist thread for injecting cache memory in a microprocessor Patrick J. Bohrer, Orran Krieger, Ramakrishnan Rajamony, Michael Rosenfield, Hazim Shafi +1 more 2012-07-24
8219746 Memory package utilizing at least two types of memories 2012-07-10
8212588 Opportunistic bus access latency Theodore Haggis, Robert Brian Likovich, Jr., James A. Mossman, Tiffany Tamaddoni-Jahromi 2012-07-03
8151042 Method and system for providing identification tags in a memory system having indeterminate data response times Paul W. Coteus, Kevin C. Gower, Warren E. Maule 2012-04-03
8145868 Method and system for providing frame start indication in a memory system having indeterminate read data latency Paul W. Coteus, Kevin C. Gower, Warren E. Maule 2012-03-27
8140764 System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory Xiaowei Shen, Balaram Sinharoy, Robert W. Wisniewski 2012-03-20
8051276 Operating system thread scheduling for optimal heat dissipation Orran Krieger, Bryan S. Rosenburg, Robert W. Wisniewski 2011-11-01
7984329 System and method for providing DRAM device-level repair via address remappings external to the device Luis A. Lastras-Montano, Darren L. Anand, Jeffrey H. Dreibelbis, Charles A. Kilmer, Warren E. Maule 2011-07-19
7962700 Systems and methods for reducing latency for accessing compressed memory using stratified compressed memory architectures and organization Peter A. Franaszek, Luis A. Lastras-Montano 2011-06-14
7934061 Methods and arrangements to manage on-chip memory to reduce memory latency Dilma M. Da Silva, Elmootazbellah Nabil Elnozahy, Orran Krieger, Hazim Shafi, Xiaowei Shen +1 more 2011-04-26
7913041 Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint Xiaowei Shen, Balaram Sinharoy, Robert W. Wisniewski 2011-03-22
7890676 Memory systems for automated computing machinery Daniel M. Dreps, Kevin C. Gower, Warren E. Maule 2011-02-15
7685392 Providing indeterminate read data latency in a memory system Paul W. Coteus, Kevin C. Gower, Warren E. Maule 2010-03-23
7640386 Systems and methods for providing memory modules with multiple hub devices Paul W. Coteus, Warren E. Maule, Edward J. Seminaro 2009-12-29
7636833 Method for selecting memory busses according to physical memory organization information associated with virtual address translation tables 2009-12-22
7636813 Systems and methods for providing remote pre-fetch buffers 2009-12-22
7627732 Memory systems for automated computing machinery Paul W. Coteus, Kevin C. Gower 2009-12-01
7624245 Memory systems for automated computing machinery Paul W. Coteus, Kevin C. Gower 2009-11-24
7610541 Computer compressed memory system and method for storing and retrieving data in a processing system Peter A. Franaszek 2009-10-27
7594055 Systems and methods for providing distributed technology independent memory controllers Kevin C. Gower, Warren E. Maule 2009-09-22